Semiconductor Memory Device Trench Gate Recess Uniformity
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Solution Overview
Problem
In semiconductor memory devices with trench gate structures, the increasing aspect ratio of word lines and shrinking repeating pitch make it difficult to form uniform recesses and maintain electrical connectivity, leading to potential electrical disconnection and poor hole processing.
Innovation Solution
The method involves forming a first conductive layer with a thickness that allows it to be buried inside recesses, ensuring a sufficient thickness on end silicon regions to prevent electrical disconnection, and using anisotropic dry etching to control the layer's thickness and create a step structure that reduces the aspect ratio of contacts, thereby improving connectivity and hole processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the repeating pitch of word lines is reduced to miniaturize the device, then device size is reduced, but forming uniform recesses becomes physically difficult
Solution Approach 1:
The patent segments the semiconductor substrate into distinct regions: memory cell regions with trench gate structures and end regions with planar transistors. This segmentation allows different transistor structures to coexist on the same substrate, enabling the use of planar transistors in end regions where uniform recess formation is difficult, while maintaining trench gate structures in memory cell regions where miniaturization is critical.
Solution Approach 2:
The patent applies different transistor structures to different locations on the substrate. End regions use planar transistors with simpler recess formation, while memory cell regions use trench gate structures. This local differentiation allows each region to be optimized for its specific requirements, solving the uniformity problem in end regions while maintaining miniaturization in memory cell regions.
2Productivity
If the aspect ratio of word lines increases due to miniaturization, then device density increases, but electrical connectivity and hole processing deteriorate
Solution Approach 1:
The patent divides the device into memory cell regions with high-density trench gate structures and end regions with planar transistors that have lower aspect ratios. This segmentation ensures that critical electrical connections in end regions are maintained with simpler structures, while high density is achieved in memory cell regions where the trench gate structures are less critical for connectivity.
Solution Approach 2:
The patent introduces dummy capacitors as intermediary structures in end regions. These dummy capacitors serve as mediators that maintain the electrical connection path and provide mechanical support, effectively reducing the impact of high aspect ratios on electrical connectivity while allowing the memory cell regions to maintain high density trench gate structures.
3Ease of manufacture
If the aspect ratio of contacts is reduced to improve hole processing, then manufacturing becomes easier, but device miniaturization is compromised
Solution Approach 1:
The patent segments contacts into two types: contacts in memory cell regions that follow the trench gate structure with higher aspect ratios, and contacts in end regions that use planar transistor structures with lower aspect ratios. This segmentation allows easier hole processing in end regions while maintaining miniaturization in memory cell regions where the higher aspect ratio contacts are acceptable due to the smaller number and less critical nature of connections.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures reliable electrical connectivity and effective hole processing by maintaining a sufficient thickness of the conductive layer on end silicon regions and reducing the aspect ratio of contacts, preventing electrical disconnection and enhancing the manufacturing process.
Implementation Method 1
anisotropic dry etching to control the layer's thickness and create a step structure
Data Source
AI summary
A semiconductor memory device includes a memory cell region; a memory mat end region; a memory mat including the memory cell region and the memory mat region; a plurality of first silicon regions arranged in the memory cell region; a second silicon region arranged in the memory mat end region; a first conductive layer provided in the memory cell region and the memory mat end region; and wherein upper surface position of the second silicon region in the memory mat end region is higher than the upper surface position of the first silicon region in the memory cell region; and wherein the upper surface position of the first conductive layer in the memory mat end region is higher than the upper surface position of the first conductive layer in the memory cell region.