Memory Device TSV Control Signal Sampling
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Solution Overview
Problem
In three-dimensional memory devices, variations in process, voltage, and temperature cause timing differences in signal output from stacked memory dies, making it difficult to operate at high speeds and increasing the area of buffer dies used for compensation.
Innovation Solution
A memory device that samples data using control signals transmitted through through silicon vias (TSVs), with FIFO circuits and a calibration unit to generate delay codes and control signals, synchronizing data output across memory dies and buffer dies to compensate for latency and maintain uniform capture margins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory dies are stacked to increase integration, then storage capacity increases, but timing synchronization becomes difficult due to process, voltage, and temperature variations
Solution Approach 1:
The calibration unit performs preliminary timing calibration by measuring path latencies and generating delay codes before normal operation. These delay codes are stored and used to pre-adjust the timing of control signals sent to each memory die, compensating for PVT variations before data transfer begins, thus achieving synchronization without affecting storage capacity
Solution Approach 2:
The system dynamically adjusts the delay parameter of control signals based on calibrated latency measurements. By changing the timing parameter of control signals transmitted through TSVs to different memory dies, the system compensates for process, voltage, and temperature variations, achieving precise timing synchronization while maintaining high storage capacity
2Manufacturing precision
If buffer die area is increased to compensate for timing variations, then timing synchronization improves, but device area increases
Solution Approach 1:
The timing calibration and delay control functions are extracted from the buffer die and implemented in the memory dies themselves. Each memory die contains its own delay control circuit that uses calibrated delay codes to adjust its timing independently, eliminating the need for a large buffer die and reducing overall device area while maintaining synchronization precision
Solution Approach 2:
Each memory die performs self-calibration and self-adjustment of timing using its own delay control circuit and the calibrated delay codes. This self-service approach eliminates the need for external buffer circuits to compensate for timing variations, significantly reducing the buffer die area while achieving precise timing synchronization across all memory dies
3Manufacturing precision
If control signals are transmitted through TSVs, then data sampling synchronization improves, but signal path latency varies
Solution Approach 1:
The calibration unit measures the actual latency of control signals transmitted through TSVs to each memory die and uses this feedback information to generate appropriate delay codes. These delay codes are then used to adjust the timing of control signals, compensating for varying path latencies and achieving synchronized data sampling across all memory dies
Data Source
AI summary
A memory die of a memory device includes a first first-in first-out (FIFO) circuit that samples data output from a memory cell array and outputs the data to a buffer die through a first through silicon via, based on a control signal transmitted from the buffer die. A buffer die of the memory device includes a second FIFO circuit that samples the data output from the first FIFO unit based on the control signal transmitted from the memory die through a second through silicon via, a calibration circuit that generates a delay code, based on a latency of a path from the buffer die to the first FIFO circuit and from the first FIFO circuit to the second FIFO circuit, and a delay control circuit that generates the control signal transmitted to the memory die through a third through silicon via, based on the read command and the delay code.