Semiconductor Memory Device Two-Stage Write Operation
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Solution Overview
Problem
Current semiconductor memory devices face challenges in reliably writing and reading 3-bit data due to variations in threshold voltage caused by initial fall and parasitic capacitance between memory cells, leading to increased error bits and reduced data reliability.
Innovation Solution
A semiconductor memory device employing a two-stage write operation using the TLC method, where the first write operation sets a rough threshold distribution, and the second write operation refines it, minimizing the influence of initial fall and parasitic capacitance, and utilizing specific data assignments and read voltages to disperse error bits and enhance error correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single-stage write operation is used to write 3-bit data, then the write operation is simple and fast, but threshold voltage variations due to initial fall and parasitic capacitance cause increased error bits and reduced data reliability
Solution Approach 1:
The write operation is divided into two distinct stages: a first write operation that writes initial data and establishes a rough threshold distribution, and a second write operation that refines the threshold distribution to reduce error bits. This segmentation allows each stage to perform a specific function, improving overall data reliability while managing complexity through structured progression.
Solution Approach 2:
The first write operation performs preliminary action by establishing an initial threshold distribution before the second write operation refines it. This preliminary establishment of threshold values prepares the memory cells for subsequent refinement, reducing the impact of initial fall and parasitic capacitance effects in the final data state.
2Productivity
If the first write operation writes all 3-bit data at once, then the write speed is fast, but threshold voltage variations increase error bits
Solution Approach 1:
The write operation is segmented into two stages with different data writing approaches. The first stage writes initial data quickly to establish baseline thresholds, while the second stage performs refined writing to correct threshold variations. This segmentation maintains overall write speed while improving reliability through structured refinement.
Solution Approach 2:
The first write operation performs preliminary data writing to establish initial threshold distributions, enabling the second write operation to focus on refinement. This preliminary action allows subsequent operations to optimize for accuracy rather than speed, reducing error bits while maintaining acceptable overall write performance.
3Reliability
If specific data assignments are used in the first write operation, then error bits are dispersed and error correction is enhanced, but the data writing process becomes more complex
Solution Approach 1:
Different data assignments are applied in different write operations based on local requirements. The first write operation uses specific data assignments optimized for establishing initial thresholds, while the second operation uses assignments optimized for refinement. This local optimization of data assignment strategies enhances error correction capability while managing complexity through context-specific approaches.
Data Source
AI summary
A semiconductor memory device includes a first memory cell for storing data using at least three levels of threshold voltages, including a first level, a second level higher than the first level and a third level higher than the second level. A first word line is connected to the first memory cell. In writing of data to the first memory cell from a state where a threshold voltage of the first memory cell is the first level, a plurality of program operations and verify operations are performed, each program operation including applying a program voltage to the first word line, each verify operation including applying a read voltage lower than the program voltage. The program operations include a program operation for the second level and a program operation for the third level, and the verify operations include a verify operation for the second level, and do not include a verify operation for the third level.