Memory Device With Variable Conductive Layer Thickness
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Solution Overview
Problem
Existing NAND flash memory devices face challenges in manufacturing yield and transistor characteristics due to variations in etching depth during slit formation, leading to defects and increased resistance values in select gate lines.
Innovation Solution
The implementation of a memory device structure with a thick conductive layer as a stopper in the slit region and a thin stopper layer in the cell region, where the source line is electrically coupled to the semiconductor layer through an opening on the memory pillar, reduces processing defects and improves transistor characteristics by minimizing unintended layer exposure and dopant diffusion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a uniform thickness conductive layer is used throughout the device, then the manufacturing process is simpler, but etching depth variations cause unintended layer exposure and defects in the slit region
Solution Approach 1:
The conductive layer is designed with different thicknesses in different regions: a first thickness in the cell region and a second (greater) thickness in the slit region. This local variation ensures that the thicker conductive layer in the slit region prevents unintended exposure during etching, while the thinner layer in the cell region maintains proper device characteristics.
2Manufacturing precision
If the conductive layer is made thicker in the slit region to prevent exposure, then manufacturing yield improves, but the overall device complexity increases
Solution Approach 1:
Rather than uniformly increasing the conductive layer thickness across the entire device, the invention applies the thicker section only where needed in the slit region. This localized approach prevents exposure and defects specifically where etching variations occur, without unnecessarily complicating the overall device structure.
3Reliability
If the source line is positioned closer to the memory pillar to reduce resistance, then electrical performance improves, but dopant diffusion to the select gate line increases
Solution Approach 1:
The conductive layer thickness is varied locally to control dopant diffusion. The thinner conductive layer in the cell region limits dopant diffusion to the select gate line, while the thicker layer in the slit region provides structural stability. This allows the source line to be positioned optimally for low resistance without excessive dopant contamination.
Data Source
AI summary
A memory device includes a substrate, first, second, and third conductive layers, a stack of fourth conductive layers, a memory pillar, and an insulator. The first, second, and third conductive layer are provided above the substrate. The stack of fourth conductive layers is provided above the third conductive layer. The memory pillar extends in the thickness direction through the stack and the third conductive layer and into the second conductive layer in a first region of the memory device. The insulator extends in a thickness direction through the stack, the third conductive layer, and the second conductive layer in a second region of the memory device. The insulator also extends in a second surface direction of the substrate. A thickness of the third conductive layer in a region through which the insulator extends is greater than a thickness of the third conductive layer in the first region.