Memory Device Conditional Verify Skip for Write Speed
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Solution Overview
Problem
The existing semiconductor memory devices face significant delays in write operations due to the numerous verify operations required, which increase the time needed to complete a write operation, especially with an increase in the number of verify operations.
Innovation Solution
The proposed memory device employs an optimal program operation and verify operation method, utilizing a 2-step verify operation with pre-verify and main verify voltages to reduce the number of verify operations within a program cycle, allowing for skipped verify operations after determining a pass, thereby reducing the overall time for write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple verify operations are performed in each program loop to ensure data accuracy, then the reliability of the write operation is improved, but the write operation time increases significantly
Solution Approach 1:
The verify operation is divided into two distinct phases: pre-verify operation performed during the program loop, and main verify operation performed after the program loop. This segmentation allows the system to perform preliminary verification during programming and reduces the need for extensive verification after completion, thereby maintaining reliability while reducing total verification time.
Solution Approach 2:
The pre-verify operation is performed in advance during the program loop to check whether the threshold voltage has reached the target level before completing the full verify sequence. This preliminary verification allows the system to determine early whether additional verify operations are necessary, reducing unnecessary verification steps and overall write time.
2Manufacturing precision
If the number of verify operations is increased to ensure complete programming, then the manufacturing precision is improved, but the productivity decreases
Solution Approach 1:
The verify operation structure is made dynamic by conditionally executing the main verify operation based on the pre-verify result. When the pre-verify determines that the threshold voltage has reached the target level, the main verify operation is skipped. This dynamic approach maintains precision when needed while maximizing speed when the target is already achieved, resolving the contradiction between manufacturing precision and productivity.
Solution Approach 2:
The system changes the verification parameter threshold by using different voltage levels for pre-verify and main verify operations. The pre-verify uses a preliminary voltage threshold to quickly assess programming status, while the main verify would use a more stringent threshold if needed. This parameter differentiation allows the system to balance precision and speed by adjusting verification strictness based on real-time programming status.
Data Source
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AI summary
A memory device includes a memory cell array including a plurality of memory cells; a voltage generator configured to generate voltages used for a program operation and a verify operation for the memory cells; and control logic configured to perform a plurality of program loops while writing data to the memory cell array, such that first to N-th (e.g., N >=1) program loops including a program operation and a verify operation are performed and at least two program loops in which the verify operation is skipped are performed when a pass/fail determination of the program operation in the N-th program loop indicates a pass.