Semiconductor Memory Device Vertical Charge Storage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor memory technologies face challenges in scaling down due to the punch-through phenomenon, increased manufacturing costs, extended manufacturing time, decreased yield, and variations in cell characteristics, particularly in multi-value and three-dimensional memory cell arrangements.
Innovation Solution
A semiconductor memory device with a columnar semiconductor portion and at least two vertically divided charge-storage layers covered by a control gate, allowing for two-bit or more data storage without relying on advanced photolithography, using a manufacturing method that includes forming a columnar semiconductor portion and charge-storage layers on a semiconductor substrate, and covering them with a control gate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-value technology is used to increase capacity per memory cell, then data storage capacity is improved, but punch-through phenomenon occurs due to reduced source-drain distance
Solution Approach 1:
The patent transitions from planar charge storage to three-dimensional charge storage by forming charge storage regions that extend vertically into the substrate. This dimensional change allows increased storage capacity without reducing source-drain distance in the planar direction, thereby avoiding punch-through phenomenon while maintaining reliability.
Solution Approach 2:
The charge storage function is segmented into multiple vertically distributed charge storage regions within a single memory cell. Each region can independently store charge, enabling multi-value storage capacity while maintaining adequate spacing between source and drain regions to prevent punch-through.
2Quantity of substance
If three-dimensional memory cell arrangement is used to increase capacity, then data storage capacity is improved, but manufacturing complexity and costs increase
Solution Approach 1:
The patent implements three-dimensional charge storage regions that extend vertically into the substrate using standard planar processing techniques combined with vertical etching and filling. This approach achieves increased capacity without requiring complex three-dimensional stacking or advanced manufacturing processes, thereby controlling manufacturing complexity and costs.
3Productivity
If memory cell area is reduced to increase integration density, then manufacturing productivity is improved, but channel width decreases causing reduced drive voltage and readout speed
Solution Approach 1:
The patent moves charge storage from a planar configuration to a three-dimensional configuration extending vertically into the substrate. This allows the channel width in the planar direction to be maintained for adequate drive voltage and readout speed, while increasing storage capacity through vertical extension, thereby improving integration density without sacrificing speed.
Data Source
AI summary
The present invention provides a semiconductor memory device including: a semiconductor substrate of a first conductivity type; and a memory cell including: (i) a columnar semiconductor portion formed on the substrate, (ii) at least two charge-storage layers formed around a periphery of the columnar semiconductor portion and divided in a direction vertical to the semiconductor substrate, and (iii) a control gate that covers at least a portion of charge-storage layers, wherein the memory cell is capable of holding two-bit or more data.