Semiconductor Memory Device Erase Operation Voltage Boosting
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Solution Overview
Problem
Current semiconductor memory devices face challenges in efficiently performing erase operations without increasing circuit area, particularly due to the need for high breakdown voltage transistors that occupy significant space when numerous bit lines are involved.
Innovation Solution
The semiconductor memory device employs capacitive coupling between drain-side select gate lines and semiconductor columns to boost the bit line voltage during erase operations, allowing for stable erase operations without the need for high breakdown voltage transistors in the sense amplifier unit, thus maintaining high integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high breakdown voltage transistors are used in the sense amplifier unit to perform erase operations, then erase operation stability is improved, but circuit area increases significantly
Solution Approach 1:
The patent introduces a voltage boosting circuit as an intermediary component between the bit line and the sense amplifier unit. This circuit includes a first transistor connected between the bit line and a first power supply line, and a second transistor connected between the bit line and a second power supply line. The voltage boosting circuit generates a boosted voltage on the bit line during erase operations, enabling stable erase operations without requiring high breakdown voltage transistors in the sense amplifier unit, thus resolving the contradiction between erase operation stability and circuit area
Solution Approach 2:
The patent changes the voltage parameter of the bit line dynamically during erase operations. By applying a boosted voltage to the bit line through the voltage boosting circuit, the electrical parameters are adjusted to enable stable erase operations. This parameter change approach allows the use of standard transistors in the sense amplifier unit rather than requiring high breakdown voltage transistors, thereby reducing circuit area while maintaining erase operation stability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables stable and efficient erase operations without increasing the circuit area, allowing for higher integration and reduced operational complexity.
Implementation Method 1
The semiconductor memory device employs capacitive coupling between drain-side select gate lines and semiconductor columns to boost the bit line voltage during erase operations
Data Source
AI summary
A semiconductor memory device includes: a first wiring; a first memory transistor; a first transistor; a second memory transistor; a second transistor; a second wiring connected to a gate electrode of the first memory transistor; a third wiring; a first gate wiring connected to a gate electrode of the first transistor; a second gate wiring connected to a gate electrode of the second transistor; and a control circuit configured to execute an erase operation that selects the first or the second memory transistor. The control circuit controls a voltage of the first gate wiring to become larger than a voltage of the second wiring and controls a voltage of the second gate wiring to become larger than the voltage of the first gate wiring in the erase operation performed with the first memory transistor selected.