Memory Device Independent Voltage Generation Circuit Power Control

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

In memory systems with shared chip enable signals, simultaneous activation of multiple memory devices leads to wasteful current consumption as only one device is accessed at a time, while the others remain active, increasing power usage unnecessarily.

Innovation Solution

Implementing independent internal voltage generation circuits for each memory device that can switch between standby, weak active, and strong active modes based on the chip enable signal and Logical Unit Number (LUN) address, allowing selective activation of internal voltage generators to optimize current consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If multiple memory devices share a chip enable signal, then device integration is improved, but current consumption increases due to simultaneous activation

Engineering Contradiction:

Improvedevice integrationVSAvoidcurrent consumption

Core Design Contradiction:

Adaptability or versatilityVSUse of energy by moving object

Solution Approach 1:

The patent divides the internal voltage generation circuit into multiple independent voltage generators, each capable of being independently controlled. This segmentation allows selective activation of individual voltage generators based on which memory device is being accessed, thereby reducing overall current consumption while maintaining the ability to integrate multiple memory devices on a single chip.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent implements dynamic control of voltage generator activation states, switching between different operational modes (standby, weak active, strong active) based on the chip enable signal and LUN address. This dynamic adjustment ensures that voltage generators are activated only when needed, optimizing the balance between device integration and current consumption.

Inventive Principle:

Principle #15Dynamics

2Speed

If all memory devices are activated simultaneously upon chip enable signal, then access readiness is improved, but power efficiency deteriorates

Engineering Contradiction:

Improveaccess readinessVSAvoidpower efficiency

Core Design Contradiction:

SpeedVSLoss of energy

Solution Approach 1:

The patent implements a preliminary action by activating only the necessary voltage generators corresponding to the selected memory device before actual memory operations begin. The mode control circuit determines which voltage generators to activate based on the LUN address, ensuring that power is prepared in advance only for the required device, thus maintaining access readiness while improving power efficiency.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent changes the operational parameters of the voltage generation circuit by implementing multiple activation modes (standby, weak active, strong active) with different current consumption levels. The mode control circuit selects the appropriate parameter set based on the chip enable signal and LUN address, optimizing the balance between access readiness and power efficiency.

Inventive Principle:

Principle #35Parameter changes

3Reliability

If multiple voltage generators are always enabled, then voltage supply reliability is improved, but current consumption increases

Engineering Contradiction:

Improvevoltage supply reliabilityVSAvoidcurrent consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent segments the voltage supply system into multiple independent voltage generators, each dedicated to specific memory devices. This segmentation allows the system to maintain voltage supply reliability for the active memory device while keeping other voltage generators in low-power states, thus reducing overall current consumption without compromising the reliability of the currently accessed device.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent dynamically adjusts the activation state of voltage generators based on operational requirements. The mode control circuit monitors the chip enable signal and LUN address to determine when voltage generators should be activated or deactivated, ensuring that voltage supply reliability is maintained only when needed, thereby optimizing the trade-off between reliability and current consumption.

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS9666297B1Memory device, memory system including the same and operation method of the memory system

Publication Date: 2017.05.30 SK HYNIX INC

AI summary

A memory system includes: a first memory device including a first internal voltage generation circuit; and a second memory device including a second internal voltage generation circuit, wherein the first memory device and the second memory device receive an identical chip enable signal, and when the chip enable signal is disabled, the first internal voltage generation circuit and the second internal voltage generation circuit are controlled in a standby mode, and when the chip enable signal is enabled, the first internal voltage generation circuit and the second internal voltage generation circuit are independently controlled to have one mode between a weak active mode and a strong active mode.