Memory Device Voltage Supply Noise Isolation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current flash memory devices face challenges in efficiently managing the voltage supply to multiple memory core chips, leading to increased manufacturing costs and potential operation failures due to high current peaks during parallel operations.
Innovation Solution
The implementation of a memory device configuration where multiple memory core chips are connected to charge pump circuits via voltage terminals, with a booster circuit and interface chip that isolates noise-generating components, allowing for averaged interconnect resistance and reduced chip size, thereby controlling voltage supply and reducing manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If multiple memory core chips are connected to charge pump circuits via voltage terminals for parallel operations, then data transfer speed is improved, but current peaks increase causing operation failures
Solution Approach 1:
The patent implements a load management circuit that preliminarily detects and manages the operational state of multiple memory core chips before parallel operations commence. This circuit monitors voltage terminal states and controls charge pump circuit activation timing, preventing simultaneous high-current draws that would cause harmful current peaks and operation failures.
2Adaptability or versatility
If multiple memory core chips are connected via interconnects to charge pump circuits, then functionality is improved, but manufacturing costs increase due to high interconnect resistance
Solution Approach 1:
The patent employs an interconnect structure designed to equalize voltage potential across multiple memory core chips. By distributing voltage terminals and charge pump circuits strategically, the system achieves averaged interconnect resistance, reducing voltage drops and signal degradation while maintaining manufacturability through standardized connection patterns.
3Device complexity
If noise-generating components are integrated with memory core chips, then device complexity is reduced, but noise interference increases affecting operation stability
Solution Approach 1:
The patent extracts noise-generating charge pump circuits from the memory core chip structure and places them on separate substrate regions or adjacent chips. This physical separation removes the harmful noise sources from proximity to sensitive memory cells, preventing interference while maintaining functional integration through controlled interconnects and voltage terminals.
Data Source
AI summary
According to one embodiment, a memory device includes: a first chip including a first circuit, first and second terminals; a second chip including a second circuit and a third terminal; and an interface chip including first and second voltage generators. The first chip is between the second chip and the interface chip. The first terminal is connected between the first circuit and the first voltage generator. A third end of the second terminal is connected to the third terminal and a fourth end of the second terminal is connected to the second voltage generator. A fifth end of the third terminal is connected to the second circuit and a sixth end of the third terminal is connected to the second voltage generator via the second terminal. The third end overlaps with the sixth end, without overlapping with the fourth end.