Memory Device Supply Voltage Line Control for Write Assist
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Solution Overview
Problem
Modern memory devices face challenges in achieving stability and write-ability while reducing power consumption and size, as smaller memory cells exhibit increased variation in behavior, leading to higher failure rates and instability, especially when operating at high speeds or low power supply voltages.
Innovation Solution
The solution leverages existing cross-capacitance between supply voltage lines and bit lines to dynamically change voltage levels during memory access operations, using control circuitry to disconnect supply voltage lines for selected columns, thereby assisting in write and read operations without the need for additional voltage generators or metal lines, thus maintaining stability and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If memory cell size is reduced to decrease device size, then device size is reduced, but variation in behavior between individual memory cells increases leading to higher failure rates
Solution Approach 1:
The patent applies local quality by providing different supply voltage levels to different columns dynamically. Specifically, the selected column receives a reduced supply voltage during write operations to improve write-ability, while non-selected columns maintain normal supply voltage to ensure stability. This localized voltage adjustment resolves the contradiction by improving reliability of write operations in small memory cells without compromising overall device stability.
Solution Approach 2:
The patent changes the supply voltage parameter dynamically based on operational requirements. During write operations, the supply voltage to the selected column is reduced to enhance write-ability of small memory cells. During read operations and idle states, normal supply voltage is maintained to ensure stability. This parameter change approach allows the system to overcome the reliability issues of scaled-down memory cells.
2Use of energy by stationary object
If supply voltage is reduced to decrease power consumption, then power consumption is reduced, but likelihood of failed operation within individual memory cells increases
Solution Approach 1:
The patent employs periodic action by dynamically switching supply voltage levels based on operational phase. During write operations, reduced supply voltage is applied temporarily to improve write-ability. During read operations and idle periods, full supply voltage is restored to maintain stability. This periodic voltage adjustment allows low power consumption during non-critical operations while ensuring high reliability during critical write operations.
Solution Approach 2:
The patent segments the memory array into selected and non-selected columns, applying different supply voltage levels to each segment. The selected column receives reduced voltage during write operations, while other columns maintain normal voltage. This segmentation allows the system to reduce overall power consumption while maintaining reliability in non-selected regions.
3Reliability
If write assist circuitry is added to improve write-ability, then write-ability is improved, but device complexity increases
Solution Approach 1:
The patent achieves multi-functionality by using the same control circuitry and voltage adjustment mechanism for both write assist and read stabilize operations. The supply voltage control circuit can dynamically adjust voltage levels for different operational modes (write, read, idle), eliminating the need for separate dedicated circuits for each function. This universal approach improves write-ability and read stability while minimizing the increase in device complexity.
Solution Approach 2:
The patent merges the write assist functionality with the existing supply voltage distribution infrastructure. Instead of adding completely separate write assist circuitry, the invention utilizes and extends the column supply voltage lines and control logic to provide both write assist (during writes) and read stabilize (during reads) functions. This merging approach reduces the complexity increase that would result from entirely separate circuits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability and speed of memory operations by stabilizing memory cells during write and read processes, reduces power consumption, and is less sensitive to temperature and voltage variations, making it suitable for low-power applications.
Implementation Method 1
for each column a capacitance existing between the associated supply voltage line and the associated at least one bit line
Data Source
AI summary
A memory device and method of operation is provided, the memory device having a plurality of memory cells arranged in at least one column, with each column having at least one bit line and a supply voltage line associated therewith. A capacitance exists between the supply voltage line and associated at least one bit line for each column. Control circuitry is used to control, for each column, connection of a voltage source to the associated supply voltage line. For a predetermined period during a memory access operation, the control circuitry disconnects the supply voltage line for at least the selected column from the voltage source, such that a voltage level on that supply voltage line changes in response to any change in voltage on the associated at least one bit line. This basic mechanism can be used to provide a variety of assist mechanisms, such as a write assist mechanism, a bit flip assist mechanism and a read assist mechanism. The technique of the present invention provides a particularly simple and power efficient technique for providing such assist mechanisms.