Semiconductor Memory Device Verification Voltage Control
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Solution Overview
Problem
As semiconductor memory devices, such as NAND flash memory, are downscaled to increase memory capacity, the proximity effect between memory cells leads to an increased width of the threshold voltage distribution, requiring higher writing and reading voltages, which in turn increases interference and chip size due to the need for more ECC gates.
Innovation Solution
The semiconductor memory device employs a word line driver to adjust verification voltages during writing stages, using a lower verify read voltage initially and increasing it later to narrow the threshold voltage distribution without altering the ECC's correcting capability, thereby reducing the need for additional gates and maintaining memory performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are downscaled to increase memory capacity, then memory capacity is improved, but the proximity effect between memory cells increases causing wider threshold voltage distribution
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting verification voltages during different writing stages. In the first writing stage, a lower verification voltage is used, while in the second writing stage, a higher verification voltage is applied. This dynamic voltage adjustment compensates for the proximity effect and narrows the threshold voltage distribution width, allowing memory cells to be downscaled while maintaining manufacturing precision.
2Reliability
If higher writing and reading voltages are applied to compensate for wider threshold voltage distribution, then data integrity is improved, but interference between adjacent memory cells increases
Solution Approach 1:
The patent segments the writing process into multiple writing stages with different verification voltages. The first writing stage uses a lower verification voltage to minimize interference, while the second writing stage uses a higher verification voltage to ensure data integrity. This segmentation allows the system to achieve both low interference and high data integrity without applying high voltages throughout the entire writing process.
Solution Approach 2:
The patent implements dynamic verification voltage adjustment based on the writing stage. The verification voltage transitions from a lower level in the first writing stage to a higher level in the second writing stage. This dynamic adjustment allows the system to optimize between interference minimization and data integrity maintenance at different stages of the writing process.
3Reliability
If ECC with high correcting capability is used to suppress writing or reading voltage increases, then data reliability is improved, but the number of gates in ECC circuit increases leading to larger chip size
Solution Approach 1:
The patent uses parameter changes in verification voltages during writing stages to narrow the threshold voltage distribution, which reduces the need for aggressive ECC. By optimizing the verification voltage profile (lower in the first stage, higher in the second stage), the system achieves better data integrity with simpler ECC requirements, thereby reducing the number of gates needed and keeping chip size manageable.
4Use of energy by moving object
If multi-level storage memory is used to reduce proximity effect, then writing and reading voltages are lowered, but threshold voltages of adjacent memory cells vary causing wider threshold voltage distribution
Solution Approach 1:
The patent applies parameter changes by using different verification voltages for different writing stages in multi-level storage. In the first writing stage, a lower verification voltage is used, and in the second writing stage, a higher verification voltage is applied. This dynamic voltage adjustment compensates for the variations in threshold voltages of adjacent memory cells, narrowing the overall threshold voltage distribution while maintaining lower operating voltages for multi-level storage.
Data Source
AI summary
A memory includes word lines, bit lines, memory cells each having a gate connected to one of the word lines, a word line driver configured to drive voltages of the word lines, and a sense amplifier configured to detect data of the memory cells via the bit lines. The memory cells are connected in series between the bit lines and a source to constitute cell string. The word line driver increases a verification voltage of any of non-selected word lines connected to non-selected memory cells in the cell string at a time of a verify operation in a certain writing loop of a writing stage. The writing stage includes a plurality of writing loops. The writing loops respectively includes a write operation to write data in a selected memory cell in the cell string and a verify operation to verify that the data are written in the selected memory cell.