Semiconductor Memory Device Wiring Structure and Voltage Application
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Solution Overview
Problem
The existing cross-point type memory devices face challenges in simplifying their wiring structure to increase memory cell integration and reduce the size of the array break, while ensuring efficient voltage application for data writing and reading.
Innovation Solution
The semiconductor memory device employs a configuration with non-selected and selected voltage application circuits disposed adjacent to each other on the substrate, using thicker connection conductors to connect bit lines to voltage generation circuits, simplifying the wiring structure and reducing the array break, thereby allowing for higher integration and efficient data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the wiring structure is simplified to increase memory cell integration, then the array break size is reduced, but the voltage application efficiency may deteriorate
Solution Approach 1:
The voltage application circuits are segmented into non-selected and selected types, positioned at different locations. Non-selected voltage application circuits are placed at both ends of the bit line, while selected voltage application circuits are positioned adjacent to memory cell arrays, allowing independent optimization of each segment's function
Solution Approach 2:
The patent transitions from a planar wiring layout to a three-dimensional structure by stacking memory cell arrays vertically and positioning voltage application circuits in different vertical layers, enabling simplified wiring while maintaining efficient voltage application through spatial separation
2Loss of energy
If thicker connection conductors are used to reduce voltage drop, then the wiring complexity increases, but the manufacturing precision requirements are improved
Solution Approach 1:
Thicker connection conductors are selectively applied only in critical paths where voltage drop is most significant, such as connections between selected voltage application circuits and memory cell arrays, while other wiring maintains standard thickness, optimizing the balance between voltage delivery and manufacturing complexity
Data Source
AI summary
A semiconductor memory device includes first and second wirings extending in a first direction and spaced apart from each other in the first direction, third wirings above the first and second wirings and extending in a second direction, fourth and fifth wirings above the third wirings, extending in the first direction, and spaced apart from each other in the second direction, a plurality of memory cells between each third wiring and each of first, second, fourth, and fifth wirings, voltage application circuits, connection conductors between the voltage application circuits and the wirings, and connection wirings that electrically connect the fourth and fifth wirings to the voltage application circuits. The voltage application circuits are arranged so that a non-selected voltage application circuit is under a space between the first and second wirings, and a selected voltage application circuit is under the first wiring.