Semiconductor Memory Device Multi-Phase Write Control
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in suppressing the spread of threshold voltage distribution after a write operation, leading to inefficiencies and potential data loss.
Innovation Solution
The semiconductor memory device employs a multi-layered word line configuration and a sequencer that executes a series of write operations, including primary, secondary, and tertiary write operations, to manage the threshold voltage distribution effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a single write operation is performed to store data in memory cells, then the write operation speed is improved, but the threshold voltage distribution spreads excessively leading to data loss
Solution Approach 1:
The write operation is segmented into multiple distinct phases: a first write operation that applies a first voltage to the control gate, and a second write operation that applies a second voltage to the control gate. This segmentation allows the write process to be performed in controlled steps, preventing excessive threshold voltage distribution spread while maintaining efficient data storage.
2Reliability
If multiple write operations are executed to reduce threshold voltage spread, then data storage reliability is improved, but the write operation time increases
Solution Approach 1:
The write operation is structured as periodic alternating actions between the first write operation and the second write operation. The sequencer alternates between applying the first voltage and the second voltage to the control gate in a systematic pattern, which efficiently reduces threshold voltage distribution spread while controlling the total operation time.
3Measurement precision
If the threshold voltage distribution is tightly controlled, then measurement precision of data states is improved, but the device complexity increases due to multiple word lines and control circuits
Solution Approach 1:
The first word line and second word line are configured to serve multiple functions: they individually control different sets of memory cells, and collectively they enable the multi-phase write operation sequence. This multi-functionality allows precise threshold voltage control without proportionally increasing device complexity, as the same word line structures are reused in different operational phases.
Data Source
AI summary
A semiconductor memory device includes a first memory pillar and a sequencer. The first memory pillar is sandwiched between a first word line and a second word line, sandwiched between a third word line and a fourth word line, sandwiched between a fifth word line and a sixth word line, includes a first memory cell facing the first word line, a second memory cell facing the second word line, a third memory cell facing the third word line, a fourth memory cell facing the fourth word line, a fifth memory cell facing the fifth word line and a sixth memory cell facing the sixth word line. The sequencer executes an erase operation on the first to sixth memory cells to enable execution of a primary write operation for the first memory cell and a primary write operation for the second memory cell at different timings.