Semiconductor Memory Device Write Controller Error Correction
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Solution Overview
Problem
Semiconductor memory devices face challenges in reducing the number of write times, which limits their design life, due to the limited number of write cycles in NAND-type flash memory, and struggle with error correction in larger units like read circuits or I/O buffers, where conventional error correction codes are inefficient.
Innovation Solution
A semiconductor memory device configuration that writes data and redundancy information across multiple chips, using a write controller and storage unit to associate identification and region specifying information, and employs a round-robin writing method to distribute data evenly across channels, constructing an error correction code to minimize write operations and handle errors effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is written to multiple HDDs with redundant information in RAID configuration, then error correction capability is improved, but the number of write operations increases
Solution Approach 1:
The invention divides data into multiple blocks and distributes them across different memory chips, with redundant information stored separately. This segmentation allows error correction without requiring all data to be rewritten when updating a single block, thus reducing the total number of write operations while maintaining reliability
Solution Approach 2:
The invention introduces a memory controller that manages the distribution and reconstruction of data across multiple chips. The controller acts as an intermediary that can reconstruct lost data blocks using redundant information from other chips, eliminating the need to rewrite all data when updating a single block
2Reliability
If conventional ECC is used for memory cell failures, then error correction is achieved, but it cannot prevent failures in larger units like read circuit or I/O buffer
Solution Approach 1:
The invention extends error correction from the traditional single-chip dimension to a multi-chip dimension. By distributing data blocks across multiple memory chips and storing redundant information separately, the system can correct errors that occur in larger units including read circuits and I/O buffers by reconstructing data from other chips
3Quantity of substance
If NAND-type flash memory is used for small area per bit and nonvolatility, then storage density is improved, but the number of write times is limited reducing design life
Solution Approach 1:
The invention combines multiple memory chips into a unified storage system where data is distributed across chips. This merging allows the system to withstand wear on individual chips better, as redundant information stored on other chips can compensate for degraded or failed blocks, thereby extending the overall design life while maintaining high storage density
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes semiconductor memory chips in which data requested to be written. The data has one or more pieces of first data in a predetermined unit. The device includes a write controller that writes the first data and redundancy information calculated by using a predetermined number of pieces of the first data and used for correcting an error in the predetermined number of pieces of the first data into different semiconductor memory chips; and a storage unit that stores identification information and region specifying information so as to be associated with each other. The identification information associates the first data and the redundancy information, and the region specifying information specifies a plurality of storage regions in the semiconductor memory chips to which the pieces of the first data and the redundancy information associated with each other are written.