Memory Device Write Leveling Strobe Delay Circuit
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Solution Overview
Problem
Current memory devices have limitations in the verification range of the write leveling operation, particularly when switching between different I/O modes like X8 and X16, which restricts the adjustment of the domain-crossing margin between clock and data strobe signals.
Innovation Solution
The memory device incorporates multiple strobe and clock delay circuits, along with replica delay circuits and multiplexers, to sample and synchronize delayed clock and strobe signals across different I/O modes, enabling the adjustment of domain-crossing margins in both X8 and X16 modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a single strobe delay circuit is used for write leveling operation, then the device complexity is reduced, but the verification range of write leveling operation is limited when switching between different I/O modes
Solution Approach 1:
The strobe delay circuit is divided into multiple independent delay circuits (first strobe delay circuit and second strobe delay circuit), each handling different I/O modes separately. This segmentation allows each circuit to be optimized for its specific mode while enabling comprehensive verification across all modes without requiring a single complex universal circuit.
Solution Approach 2:
A replica of the second strobe delay circuit is created and configured to operate in the first I/O mode. This copying approach allows the same delay circuit design to be reused across different I/O modes, increasing adaptability and verification range while avoiding the need to design entirely new circuits for each mode, thus controlling device complexity.
2Adaptability or versatility
If multiple strobe delay circuits are used to cover different I/O modes, then the verification range of write leveling operation is increased, but the device complexity increases
Solution Approach 1:
The delay circuits are designed with multi-functionality to handle different I/O modes. The first strobe delay circuit serves both the first I/O mode directly and the second I/O mode through the replica circuit. This universal design allows a single physical circuit implementation to provide verification capabilities across multiple I/O modes, reducing the need for entirely separate verification paths for each mode.
Solution Approach 2:
Instead of creating completely independent delay circuits for each I/O mode, the patent uses a replica approach where the second strobe delay circuit is copied and adapted for use in the first I/O mode. This copying strategy increases verification coverage while reusing existing circuit designs, thereby limiting the growth of device complexity.
3Manufacturing precision
If different delay circuits are used for different I/O modes, then the domain-crossing margin adjustment is improved for each mode, but the ease of operation is reduced due to mode-specific configurations
Solution Approach 1:
The write leveling operation uses feedback from sampling the domain-crossing point to automatically adjust the delay values of the strobe delay circuits. This feedback mechanism enables precise domain-crossing margin adjustment for each I/O mode without requiring manual configuration, as the system self-calibrates based on actual signal timing measurements, thereby maintaining ease of operation despite having mode-specific circuits.
Solution Approach 2:
The delay circuits are designed to be dynamically adjustable rather than fixed, allowing the delay values to be modified based on the operating I/O mode and the measured skew between clock and data strobe signals. This dynamic adaptability enables precise domain-crossing margin adjustment for each mode while the system automatically adapts to the current operating conditions, maintaining ease of operation.
Data Source
AI summary
A memory device includes a first strobe delay circuit delaying a first data strobe signal to generate a delayed first data strobe signal, a first write leveling circuit sampling a first delay clock in synchronization with the delayed first data strobe signal, a second strobe delay circuit delaying a second data strobe signal to generate a delayed second data strobe signal, a replica second strobe delay circuit delaying the first data strobe signal by a delay value obtained by replicating the second strobe delay circuit to generate a replica delayed second data strobe signal; and a second write leveling circuit sampling a second delay clock in synchronization with the delayed second data strobe signal in a first I/O mode, and sampling the second delay clock in synchronization with the replica delayed second data strobe signal in a second I/O mode.