Semiconductor Memory Device Write Operation Stabilization
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Solution Overview
Problem
Semiconductor memory devices face challenges in reducing error bits and enhancing data retention reliability due to variations in threshold voltage after programming operations, where electrons can be detrapped from the charge storage layer, leading to data retention issues and increased error rates during read operations.
Innovation Solution
The semiconductor memory device employs a specific write operation methodology involving multiple iterations of a program loop with recovery and verify operations, where select transistors are controlled to manage electric fields and prevent hot carrier injection, using a configuration of select gate lines and word lines to stabilize threshold distributions and reduce data retention effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional program operation is performed to write data in memory cell transistors, then data is stored in the charge storage layer, but electrons can be detrapped from the charge storage layer leading to threshold voltage variations and increased error bits
Solution Approach 1:
The patent applies a preliminary recovery operation before the verify operation to remove electrons from the channel that were trapped during the program operation. This preliminary action prevents threshold voltage variations by clearing trapped electrons before verification, thereby improving data retention reliability and reducing error bits without sacrificing programming effectiveness.
Solution Approach 2:
The patent implements a continuous write operation sequence consisting of program operation → recovery operation → verify operation, where the recovery operation continuously removes trapped electrons during the write process. This continuous action ensures that threshold voltage remains stable throughout the programming process, preventing electron detrapping issues and maintaining high data retention reliability.
2Productivity
If high voltage is applied to program memory cell transistors, then data is written efficiently, but hot carriers are generated and injected into select transistors causing performance degradation
Solution Approach 1:
The patent extracts hot carriers from the channel by applying a recovery voltage that creates an electric field to pull trapped electrons out of the channel and remove them to the source or drain. This extraction process prevents hot carrier injection into select transistors while maintaining efficient programming speed through the continuous program-recover-verify cycle.
Solution Approach 2:
The patent introduces a recovery operation as an intermediary step between the program operation and verify operation. This intermediary recovery operation acts as a mediator that removes trapped electrons from the channel, preventing them from causing threshold voltage variations or being injected into select transistors, thereby protecting select transistor performance while maintaining programming efficiency.
3Reliability
If multiple program loops are executed to ensure data retention, then data reliability is improved, but the write operation time increases
Solution Approach 1:
The patent implements a continuous write operation sequence where the recovery operation is seamlessly integrated between program and verify operations. This continuous action ensures that trapped electrons are removed during the programming process itself, allowing multiple program loops to be executed efficiently without significant time penalty, thereby improving data retention reliability while minimizing write operation time.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces error bits and enhances data retention reliability by stabilizing threshold distributions and preventing performance degradation of select transistors, thereby improving the overall reliability of written data in memory cell transistors.
Implementation Method 1
a control voltage is applied to a control gate of the memory cell transistor
Implementation Method 2
a read voltage is applied to a bit line coupled to the memory cell transistor, and a threshold voltage of the memory cell transistor is determined based on a current flowing through the bit line
Data Source
AI summary
A semiconductor device according to an embodiment includes first and second drain select transistors, first and second source select transistors, first and second memory cell transistors, third and fourth memory cell transistors, first and second bit lines, first to third select gate line, first and second word lines, and a controller. The controller is configured to execute, in the program loop, a program operation, a recovery operation and a verify operation in sequence. In the write operation of the first memory cell transistor, the controller is configured, at a first time of the recovery operation, to: apply a first voltage to the first select gate line; apply a second voltage to the third select gate line; and apply a third voltage to the first bit line.