Memory Device Read Voltage Optimization via Internal XOR Counting
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Solution Overview
Problem
Current memory devices face challenges in efficiently determining optimal read voltages for memory cells, leading to increased power consumption and reduced reliability due to variations in threshold voltage distributions, especially in multi-level cell systems.
Innovation Solution
A memory device with a page buffer unit and counting unit that performs XOR operations on data read at different voltage levels, counting '1' outcomes to determine optimal voltage levels, and a voltage level determining unit that automatically updates voltage levels for minimal error search operations, reducing the need for data exchange with the memory controller.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple read voltage levels are used to handle threshold voltage variations in multi-level cell systems, then reading reliability is improved, but power consumption increases
Solution Approach 1:
The memory device autonomously performs minimal error search operations to determine optimal read voltages without external controller intervention. The page buffer unit executes XOR operations and the counting unit tallies results internally, enabling the device to self-optimize read parameters and reduce unnecessary power consumption while maintaining high reading reliability through adaptive voltage selection
Solution Approach 2:
The system dynamically adjusts read voltage parameters based on threshold voltage distributions detected during minimal error search operations. By automatically determining optimal voltage levels and updating them in the voltage level determining unit, the system adapts to varying memory cell characteristics, improving reading reliability across different operational conditions without requiring excessive voltage levels
2Reliability
If manual voltage level determination through data exchange with memory controller is used, then voltage optimization is achieved, but device complexity and operation time increase
Solution Approach 1:
The patent extracts the voltage determination functionality from the external memory controller and relocates it within the memory device itself. The page buffer unit and counting unit perform XOR operations and voltage optimization internally, eliminating the need for complex data exchange protocols with the controller and reducing overall system operation complexity while maintaining optimized voltage control
Solution Approach 2:
The system performs minimal error search operations in advance to pre-determine optimal read voltages before actual data reading operations. By conducting these optimization operations beforehand within the device, the system avoids the need for complex real-time voltage determination through external controller intervention, thereby simplifying overall device operation
3Ease of manufacture
If traditional read voltage determination methods are used, then manufacturing simplicity is maintained, but reading reliability decreases due to threshold voltage variations
Solution Approach 1:
The memory device performs self-diagnosis and self-optimization by autonomously executing minimal error search operations to determine optimal read voltages. This self-service capability allows the device to adapt to threshold voltage variations without requiring complex manufacturing adjustments or external controller involvement, thereby maintaining manufacturing simplicity while significantly improving reading reliability
Solution Approach 2:
The system transitions from static, fixed read voltage approaches to dynamic voltage determination through minimal error search operations. The voltage level determining unit automatically updates optimal voltage levels based on detected threshold voltage distributions, enabling the system to adapt to manufacturing variations and maintain high reading reliability without complicating the manufacturing process
Data Source
AI summary
A memory device includes a memory cell array having a plurality of memory cells, and a page buffer unit including a plurality of page buffers configured to store a plurality of pieces of data sequentially read from some of the plurality of memory cells at different read voltage levels, respectively, and to perform a logic operation on the plurality of pieces of data, respectively. The memory device further includes a counting unit configured to count the number of memory cells that exist in each of a plurality of sections defined by the different read voltage levels, based on results of the logic operation.