Memory Interface DFE Tap Synchronization
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Solution Overview
Problem
Current memory interfaces face challenges in data recovery due to inter-symbol interference and varying DFE tap settings during training, leading to prolonged training procedures as the number of DIMMs increases, causing user dissatisfaction.
Innovation Solution
An information handling system determines an average tap setting for each byte group and adjusts anomalous tap settings to the average value if they differ by more than a threshold, reducing the need for prolonged retraining by synchronizing tap settings across lanes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of DIMMs is increased to provide more memory capacity, then memory capacity is improved, but training time is prolonged due to varying DFE tap settings across lanes
Solution Approach 1:
The patent changes the tap setting parameter from individual lane-specific values to a unified average value across all lanes in a byte group. By calculating the average tap setting and applying it uniformly to all lanes, the system resolves variations that cause prolonged training, thereby reducing training time while maintaining memory capacity expansion
Solution Approach 2:
The patent enforces homogeneity by setting all lanes in a byte group to the same average tap setting value. This uniformity across previously varying lanes eliminates the need for extended training procedures to accommodate lane variations, thus reducing training time while supporting increased DIMM quantities
2Measurement precision
If individual DFE tap settings are optimized for each lane during training, then data recovery accuracy is improved, but training procedure duration is prolonged
Solution Approach 1:
The patent merges the individual lane tap settings into a single average value for the entire byte group. By combining multiple lane-specific parameters into one unified parameter, the system maintains adequate data recovery accuracy across all lanes while significantly reducing the training procedure duration
Solution Approach 2:
The average tap setting serves as a universal parameter for all lanes in the byte group, replacing the need for lane-specific optimizations. This universal parameter achieves satisfactory data recovery across multiple lanes simultaneously, reducing the overall training time while maintaining adequate accuracy
3Reliability
If lane-specific DFE tap settings are used, then equalization performance is improved, but initialization time increases due to retraining requirements
Solution Approach 1:
The patent changes the equalization parameter from lane-specific tap settings to a unified average tap setting. This parameter change maintains sufficient equalization performance across all lanes while eliminating the need for repeated retraining, thus reducing initialization time
Data Source
AI summary
An information handling system includes a memory controller and a dual in-line memory module (DIMM) coupled to the memory controller by a memory channel. The memory channel includes a plurality of single-ended multi-drop lanes arranged in a byte group. The information handling system determines, for each lane in the byte group, a tap setting for an associated decision feedback equalizer (DFE) of each lane. The information handling system further determines an average value for the tap settings for the lanes in the byte group, determines that a first tap setting for a first lane is different from the average value by greater than a threshold, and sets the first tap setting to the average value in response to determining that the first tap setting is different from the average value by greater than the threshold.