Independent Local and Global Clocks for Faster Memory DFT
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Solution Overview
Problem
Existing memory devices face inefficiencies in DFT operations due to the generation of internal clocks using a common clock generator, leading to significant timing penalties and limited speed during DFT operations.
Innovation Solution
The implementation of independent clock generators for local and global clock signals allows for separate tuning of power, performance, and area (PPA) in DFT mode without affecting mission mode operations, by using a first clock generator for local clock signals and a second clock generator for global clock signals, with logic gates to manage their independent generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a common clock generator is used for both local and global clock signals, then device complexity is reduced, but DFT operation speed deteriorates due to significant timing penalties
Solution Approach 1:
The patent divides the clock generation system into two independent clock generators: a first clock generator for local clock signals and a second clock generator for global clock signals. This segmentation allows each generator to be optimized independently, resolving the contradiction by reducing DFT operation timing penalties while maintaining manageable device complexity through modular architecture.
Solution Approach 2:
The patent implements dynamic clock signal generation where the first and second clock generators can operate independently with different timing characteristics. This dynamic approach allows the system to adapt clock signals to specific operational modes (mission mode vs. DFT mode), improving DFT operation speed without permanently increasing overall device complexity.
2Speed
If independent clock generators are used for local and global clock signals, then DFT operation speed is improved, but device complexity increases
Solution Approach 1:
By segmenting the clock generation into two independent generators, the patent achieves improved DFT operation speed while managing complexity through modular design. Each generator handles specific clock signal requirements, avoiding the need for a single complex generator that would handle all timing requirements.
Solution Approach 2:
The first clock generator serves dual purposes by providing clock signals for both mission mode operations and DFT mode operations. This multi-functionality reduces the need for additional dedicated clock generators, thereby improving DFT operation speed while minimizing the increase in device complexity.
3Ease of manufacture
If a common clock generator is used, then manufacturing is simpler, but timing precision during DFT operations deteriorates
Solution Approach 1:
The patent segments clock generation into two independent generators, allowing each to be optimized for specific timing requirements. This improves timing precision during DFT operations while maintaining ease of manufacture through standardized, independent generator modules that can be implemented using conventional design approaches.
Solution Approach 2:
The patent applies local quality by providing different clock signal characteristics to different parts of the system: local clock signals for memory array operations and global clock signals for control logic. This localized optimization improves timing precision for DFT operations without requiring a complete redesign of the entire clock generation system.
Data Source
AI summary
A memory device includes a plurality of memory cells arranged in an array, a first clock generator connected to the plurality of memory cells and configured to generate a local clock signal to be provided to the plurality of memory cells, a second clock generator connected to an input/output interface connected to the plurality of memory cells, the second clock generator configured to generate a global clock signal to be provided to the input/output interface, and one or more logic gates connected to at least one of the first clock generator or the second clock generator, wherein the one or more logic gates allow the local clock signal and the global clock signal to be output independently.