Cross-Point Memory Die Area Optimization via Boundary Tile Integration
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Solution Overview
Problem
In three-dimensional cross-point memory architectures, regions dedicated to support circuitry increase the physical dimensions of memory devices without enhancing capacity, leading to inefficient utilization of die area.
Innovation Solution
The solution involves reducing the size of boundary tiles and potentially eliminating them in a quilt architecture, positioning boundary tiles on only one side of the memory array, and integrating column lines and decoders within these tiles, while placing memory cells above the boundary tiles to reduce the area devoted to support components and increase accessible memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If regions dedicated to support circuitry are included in the memory device, then the memory device can provide necessary control and access functions, but the physical dimensions of the memory device increase without enhancing capacity
Solution Approach 1:
The patent combines support circuitry functions (decoders, sense amplifiers) directly within the boundary tiles that also contain memory cells, rather than having separate dedicated support regions. This integration allows the same physical space to serve dual purposes: storing data and providing access control, thereby reducing overall die area while maintaining full memory access functionality.
Solution Approach 2:
Boundary tiles are designed to serve multiple functions simultaneously: they contain memory cells for data storage, include decoder circuits for address decoding, and provide sense amplifier functions for data reading. This multi-functionality eliminates the need for separate dedicated support circuitry regions, reducing die area while preserving all necessary memory operations.
2Adaptability or versatility
If boundary tiles are positioned on all sides of the memory array, then all memory cells can be accessed, but the die area is increased due to redundant support components
Solution Approach 1:
The patent extracts redundant support circuitry from boundary tiles by implementing a wraparound addressing scheme where the last column of one memory tile can be accessed by the first column of the next tile. This eliminates the need for duplicate decoder and sense amplifier circuits in adjacent boundary tiles, reducing die area while maintaining complete memory cell accessibility through the wraparound address mapping.
Solution Approach 2:
Instead of providing separate access paths for each boundary tile, the patent inverts the approach by allowing memory cells in one tile to be accessed through the decoder of an adjacent tile via wraparound addressing. This reverse access method eliminates redundant support components in boundary tiles while ensuring all memory cells remain accessible.
3Area of stationary object
If memory cells are positioned above boundary tiles, then storage capacity is reduced, but die area is optimized and accessibility is improved
Solution Approach 1:
The patent changes the addressing parameters (row and column indices) to implement wraparound addressing, where the last column index wraps to the first column index of the next tile. This parameter transformation allows memory cells physically located in boundary regions to be logically addressed as if they were in interior regions, effectively increasing accessible capacity without requiring additional physical memory cells.
Data Source
AI summary
Methods, systems, and apparatus that support efficient utilization of die area for cross-point memory architecture are described. A memory array may include active memory cells overlying each portion of the substrate that includes certain types of support circuitry, such as decoders and sense amplifiers. Boundary tiles, which may be portions of an array having a different configuration from other portions of the array, may be positioned on one side of an array of memory tiles. The boundary tiles may include support components to access both memory cells of neighboring memory tiles and memory cells overlying the boundary tiles. Column lines and column line decoders may be integrated as part of a boundary tile. Access lines, such as row lines may be truncated or omitted at or near borders of the memory portion of the memory device.