Memory Die Inactive Area Balancing for Bad Block Uniformity

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Solution Overview

Problem

Memory systems experience performance disparities due to varying bad block sizes across multiple memory dies, leading to inefficiencies in data input/output operations and increased overheads in scheduling and resource management.

Innovation Solution

A controller adjusts inactive area sizes and operational parameters across memory dies to equalize performance, including setting inactive areas based on bad block sizes and managing over provisioning areas to ensure uniform data input/output performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If bad blocks are present in memory dies, then data storage capacity is reduced, but performance uniformity across multiple memory dies deteriorates

Engineering Contradiction:
Improvedata storage capacityVSAvoidperformance uniformity
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent applies local quality by adjusting inactive area sizes differently for each memory die based on its specific bad block characteristics. Each memory die receives a customized inactive area configuration that compensates for its unique defect profile, thereby achieving performance uniformity while preserving as much usable storage capacity as possible across all dies.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent changes the parameter of inactive area size dynamically based on bad block detection results. By varying this parameter across different memory dies according to their respective bad block sizes, the system balances storage capacity retention with performance uniformity, resolving the contradiction between reliability and productivity.

Inventive Principle:
Principle #35Parameter changes

2Productivity

If inactive area sizes are adjusted to compensate for bad blocks, then performance uniformity is improved, but device complexity increases

Engineering Contradiction:
Improveperformance uniformityVSAvoidcontroller complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by performing bad block detection and inactive area calculation before actual data storage operations begin. The controller pre-determines the appropriate inactive area sizes for each memory die based on detected bad blocks, so that during normal operation, the controller simply needs to enforce these pre-calculated configurations, thereby reducing real-time control complexity while maintaining performance uniformity.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system implements self-service by enabling the memory system to automatically detect bad blocks and configure appropriate inactive areas without external intervention. The controller autonomously performs bad block identification, calculates compensatory inactive area sizes, and applies these configurations to achieve performance uniformity, thereby managing device complexity internally rather than requiring external management.

Inventive Principle:
Principle #25Self-service

3Productivity

If different inactive area sizes are allocated to memory dies with different bad block sizes, then data input/output performance is equalized, but scheduling complexity increases

Engineering Contradiction:
Improvedata input/output performanceVSAvoidscheduling complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by pre-calculating and pre-allocating appropriate inactive area sizes for each memory die based on its bad block characteristics before data input/output operations commence. This preliminary configuration ensures that during actual data processing, each memory die operates with optimized parameters, achieving performance equalization while minimizing real-time scheduling complexity through advance preparation.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20250370624A1Apparatus and method for reducing or adjusting unbalanced performance based on bad blocks in a memory device
Publication Date: 2025.12.04 SK HYNIX INC
  • US20250370624A1 patent drawing
  • US20250370624A1 patent drawing
  • US20250370624A1 patent drawing

AI summary

A memory system includes a memory device comprising plural memory dies, each memory die comprising plural memory blocks and including an active area and an inactive area and a controller configured to adjust sums of a bad block size and an inactive area size in the plural memory dies to be equal to each other based on a bad block occurring or found in the plural memory dies.