Memory Die Channel Segmentation for Data Access
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Solution Overview
Problem
Current memory devices face challenges in enhancing data access rates while maintaining compatibility with a wide range of host devices without increasing the physical area or requiring enhanced host device designs, particularly in configurations involving multiple memory dies.
Innovation Solution
The system configures memory devices to communicate using increased data per-pin per-access and multiple channels, with channels divided at sub-x8 granularity, allowing each memory die to operate independently, and employs auxiliary pins for error detection and data coding, ensuring compatibility and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If memory devices use traditional communication configurations, then host device compatibility is maintained, but data access rates are limited
Solution Approach 1:
The patent segments the communication interface into multiple independent channels (e.g., Channel 0, Channel 1, Channel 2, Channel 3), each capable of operating at different data rates. This allows the memory device to present a lower data rate interface to legacy host devices while internally utilizing higher data rate channels to achieve improved overall data access rates. The segmentation enables backward compatibility while pursuing performance enhancement.
Solution Approach 2:
The patent introduces a new dimension of communication by implementing multiple channels with different data rates simultaneously. Instead of a single communication path, the system creates parallel communication dimensions where some channels operate at traditional speeds for compatibility while others operate at enhanced speeds for performance, effectively adding a rate-dimension to the communication architecture.
2Productivity
If memory device area is increased to accommodate more pins, then data transfer capability is enhanced, but physical footprint expands
Solution Approach 1:
The patent implements multi-functionality in the pin assignments where certain pins serve multiple purposes across different channels and operational modes. For example, data pins can be dynamically assigned to different channels based on the operational mode, and auxiliary pins can serve both error detection and data coding functions. This universal usage of pins enhances data transfer capability without requiring additional physical pins or expanding the device area.
Solution Approach 2:
The patent utilizes parameter changes by dynamically configuring the operational mode (full I/O mode or half I/O mode) to alter how pins are utilized. In full I/O mode, all data pins are actively used for data transfer, while in half I/O mode, only a subset is used. This dynamic parameter adjustment allows the system to maximize data transfer capability within the existing pin constraints without expanding the physical footprint.
3Speed
If multiple memory dies are used to increase storage capacity, then data access rate can be improved, but device complexity increases
Solution Approach 1:
The patent merges multiple memory dies into a unified communication interface by assigning each die to a specific channel (e.g., Die 0 to Channel 0, Die 1 to Channel 1). This merging approach allows the memory device to present a simplified single interface to the host while internally coordinating multiple dies across different channels. The host sees a unified device rather than multiple separate dies, reducing perceived complexity while maintaining improved data access rates through parallel die operation.
Data Source
AI summary
Methods, systems, and devices for multiple memory die techniques are described. A memory device may include multiple memory dies and may be configured to communicate with a host device. For example, each memory die may be coupled with a set of data pins that includes respective subsets of data pins (e.g., a set of eight data pins having two subsets of four data pins). Further, each memory die may have one or more auxiliary pins used for channel coding information for data communicated over one or more of the subsets of data pins. In some cases, each memory die may include one or more additional auxiliary pins, which may be used for channel coding information for a respective subset of data pins or multiple subsets of data pins. The channel coding information associated with the auxiliary pin(s) may include error detection code information, data coding information, or any combination thereof.