Memory Die Clock Offset Compensation Using Delay Adjusters
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Solution Overview
Problem
In multi-die memory devices, clock signal timing variations due to channel delays and internal process variations lead to undesirable WCK/CK offsets, reducing the timing budget for memory operations, and traditional methods like write-leveling are ineffective for memory devices with multiple memory dice having different offsets and polarities.
Innovation Solution
Implementing die-specific offset adjustments, both globally and internally within each memory die, using delay adjusters to compensate for individual offsets, ensuring synchronized clock signals for accurate memory access operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional write-leveling methods are used to compensate for clock signal timing variations, then timing adjustments can be made at the write level, but the method becomes ineffective when multiple memory dice have different offsets and polarities
Solution Approach 1:
The patent divides the timing compensation into two independent segments: global write-leveling adjustment (applied to all dies) and die-specific offset adjustment (applied individually to each die). This segmentation allows the system to handle both common timing issues and individual die variations simultaneously, resolving the contradiction between general timing compensation and multi-die specific requirements
Solution Approach 2:
The patent introduces die-specific offset adjustment mechanisms that are tailored to each individual memory die's unique timing characteristics. Each die receives customized delay adjustments based on its specific WCK/CK offset and polarity, rather than applying a uniform adjustment across all dies. This local quality approach enables effective timing compensation in multi-die devices where global methods fail
2Reliability
If die-specific offset adjustments are implemented, then timing variations can be compensated for in multi-die devices, but the device complexity increases
Solution Approach 1:
The patent implements preliminary action by performing offset calibration and delay adjustment during the manufacturing process or initial system setup. The die-specific offset values are determined and stored in advance, allowing the timing compensation to be automatically applied during normal operation without requiring complex real-time measurement and adjustment mechanisms. This preliminary calibration simplifies the ongoing operation while maintaining high timing accuracy
Solution Approach 2:
The patent employs feedback mechanisms where the system monitors the actual timing relationships between WCK and CK signals and automatically adjusts the delay elements accordingly. The phase detector measures the offset and polarity, and the delay adjuster modifies the timing to compensate for variations. This closed-loop feedback system maintains timing accuracy while using relatively simple adjustment circuitry compared to open-loop methods
Data Source
AI summary
Methods, systems, and devices for system-level timing budget improvements are described. Each memory die in a memory device may determine an offset between its system clock signal and its data clock signal. The offsets of each memory die in the memory device may be different; e.g., having different magnitudes and/or polarities. A memory die in the memory device may adjust its own data clock signal by a delay that is based on the offsets of two or more memory die in the device. The memory die may adjust its data clock signal by setting a fuse in a delay adjuster on the memory die. Adjusting the data clock signal may match an offset of a first memory die with an offset of a second memory die.