Memory Die Error Pattern Detection and Selective Region Erasure

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Solution Overview

Problem

Memory modules, such as DRAM, often experience errors due to faulty memory cells, leading to data corruption and reduced redundancy, impacting system operation.

Innovation Solution

A method where a controller analyzes error patterns to identify failing regions within a die, marking only those regions as 'erased' to maintain data integrity and redundancy, using error counters to adjust granularity for precise failure determination and minimize degraded redundancy.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the entire die is marked as erased when errors are detected, then data integrity is maintained, but memory capacity is reduced due to loss of redundant regions

Engineering Contradiction:
Improvedata integrityVSAvoidmemory capacity
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The die is divided into multiple independently addressable regions, allowing selective erasing of only the faulty region rather than the entire die. This segmentation enables preservation of healthy memory regions while isolating errors, thus maintaining both data integrity and maximizing usable memory capacity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Error handling is applied locally to specific regions rather than globally to the entire die. The system identifies and marks only the affected region as erased, leaving other regions operational. This local quality approach ensures that data integrity is maintained in the faulty region while preserving capacity in healthy regions.

Inventive Principle:
Principle #3Local quality

2Reliability

If error correction is applied aggressively to all regions, then data integrity is improved, but system performance degrades due to increased correction overhead

Engineering Contradiction:
Improvedata integrityVSAvoidsystem performance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

Instead of applying error correction uniformly to all regions, the system applies correction only where necessary - specifically to regions that have not been marked as erased. This partial action approach maintains data integrity for at-risk regions while avoiding unnecessary correction overhead in healthy regions, thus preserving system performance.

Inventive Principle:
Principle #16Partial or excessive action

3Measurement precision

If the granularity of error tracking is fine-grained at the region level, then measurement precision of failures is improved, but device complexity increases due to additional tracking mechanisms

Engineering Contradiction:
Improvefailure detection precisionVSAvoiderror tracking complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The error tracking system uses self-service mechanisms where each region maintains its own error count in dedicated error counters. The controller simply reads these pre-maintained counters to identify faulty regions, eliminating the need for complex external tracking mechanisms. This approach achieves fine-grained failure detection precision while minimizing device complexity through decentralized, autonomous region-level tracking.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS10275307B2Detection of error patterns in memory dies
Publication Date: 2019.04.30 HEWLETT PACKARD ENTERPRISE DEV LP
  • US10275307B2 patent drawing
  • US10275307B2 patent drawing
  • US10275307B2 patent drawing

AI summary

A method is provided. In an example, the method includes identifying a memory module that includes a plurality of memory dies. Each memory die of the plurality of memory dies includes a plurality of memory regions, and each memory die of the plurality of memory dies services a respective portion of a data access. An error pattern is detected in a first memory region of the plurality of memory regions. The first memory region is associated with a first memory die of the plurality of memory dies. Based on the detected error pattern, the first memory region of the first memory die is marked as erased without marking a second memory region of the first memory die as erased.