Memory Die Family Threshold Voltage Offset Bin Selection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory sub-systems fail to adequately address the temporal voltage shift caused by slow charge loss in memory cells, leading to increased raw bit error rates during read operations, due to inefficient strategies and computational or storage inefficiencies.
Innovation Solution
The memory sub-system employs die family-based error avoidance strategies by tracking temporal voltage shift for programmed blocks grouped by block families and applying appropriate voltage offsets to base read levels, reducing the need for extensive calibration and improving bit error rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If extensive calibration operations are performed to address temporal voltage shift, then bit error rate improves, but system complexity and processing time increase
Solution Approach 1:
The patent segments the calibration process by grouping dies into die families based on their threshold voltage offset characteristics. Instead of calibrating each die individually, the system performs calibration on representative dies from each family and applies the same calibration parameters to all dies in that family. This segmentation reduces the number of calibration operations from N (total dies) to M (number of die families), where M << N, thereby reducing system complexity while maintaining reliability.
Solution Approach 2:
The patent performs preliminary grouping of dies into die families based on threshold voltage offset characteristics before calibration. By pre-organizing dies into families with similar characteristics, the system prepares the data structure needed for efficient calibration. This preliminary action allows the calibration process to operate on grouped data rather than individual dies, reducing processing time and complexity while still achieving the required bit error rate performance.
2Reliability
If individual die calibration is performed to reduce bit error rate, then reliability improves, but processing time and productivity decrease
Solution Approach 1:
The patent merges the calibration operations for multiple dies by identifying die families with similar threshold voltage offset characteristics. Once a representative die from a family is calibrated, the same calibration parameters are merged and applied to all other dies in that family. This merging of calibration operations maintains the reliability improvement from calibration while dramatically increasing productivity by processing entire families simultaneously rather than sequentially calibrating each die individually.
3Measurement precision
If comprehensive voltage offset tracking is implemented for all dies, then measurement precision improves, but storage requirements and device complexity increase
Solution Approach 1:
The patent applies universality by creating die families where a single set of calibration parameters serves multiple dies simultaneously. Instead of maintaining separate voltage offset tracking data for each die, the system maintains one set of parameters per die family that universally applies to all members. This multi-functional approach preserves measurement precision for voltage distribution tracking while reducing metadata storage requirements from O(N) to O(M), where M is the number of die families.
Data Source
AI summary
A method includes associating, by a processing device, a set of dies of a block family with a die family, wherein the block family is associated with a first threshold voltage offset bin for voltage offsets to be applied in a read operation; and responsive to detecting a triggering event, associating each die of the set of dies with a second threshold voltage offset bin for voltage offsets to be applied in a read operation, wherein the second threshold voltage offset bin is selected based on a representative die of the set of dies associated with the die family.