Stack-Aware Memory Die Numbering Circuit for 3DIC Reliability
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Solution Overview
Problem
Existing three-dimensional integrated circuits (3DIC) face errors due to the need for manual programming of identification numbers on each memory die during fabrication, which increases the likelihood of misplacement and errors in the stack.
Innovation Solution
Each memory die in the 3DIC system automatically generates a number signal corresponding to its level in the stack using a numbering circuit with serially coupled calculating circuits, allowing for internal and automatic numbering without additional initialization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If identification numbers are programmed or set to each die through hardwires or e-fuses during fabrication, then each die can be correctly accessed in the 3DIC stack, but the possibility of errors increases since each die must be manually labeled and placed on a corresponding level
Solution Approach 1:
Each memory die automatically generates its own level identification number through the numbering circuit without requiring external programming or manual labeling. The circuit self-determines the die's position in the stack by counting clock cycles, eliminating the need for human intervention and reducing placement errors.
Solution Approach 2:
The identification number is generated in advance during the operational phase rather than being pre-programmed during fabrication. The numbering circuit prepares the identification signal dynamically based on the stack configuration, allowing flexibility without requiring pre-labeling of each die.
2Adaptability or versatility
If manual programming of identification numbers is performed on each memory die during fabrication, then each die can be uniquely identified, but the design complexity and flexibility are reduced
Solution Approach 1:
The numbering circuit is designed to be universal and can be applied to any memory die in the stack without modification. The same circuit structure automatically adapts to different stack configurations and levels, providing versatility without requiring custom programming for each die.
Solution Approach 2:
The identification number is dynamically generated based on the operational context rather than being static and pre-determined. The numbering circuit adjusts the identification signal according to the actual stack configuration, enabling flexible adaptation to different memory system architectures.
3Ease of operation
If each die is labeled with identification number during fabrication, then correct access is enabled, but additional circuitry and initialization steps are required
Solution Approach 1:
The memory die automatically generates its own identification number without requiring external programming circuits or initialization sequences. The numbering circuit self-configures based on the stack topology, simplifying the overall system operation while maintaining ease of access.
Solution Approach 2:
The numbering function is merged with the existing memory die structure, integrating the identification generation capability within the standard memory cell design. This combination eliminates the need for separate programming circuits and initialization steps while maintaining ease of operation.
Data Source
AI summary
Memory systems and memory dies are provided. The memory system of the present disclosure includes a plurality of memory dies stacked within the memory system. Each memory die includes a numbering circuit configured to generate an output number signal according to an input number signal. The numbering circuit includes a plurality of calculating circuits coupled in series. A current stage calculating circuit is configured to receive a first output bit from a previous stage calculating circuit and a corresponding bit of the input number signal to generate the first output bit and a second output bit as a correspond bit of the output number signal.