Memory Die Interconnects for Wider LPDDR5 Channels and PHY Training
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Solution Overview
Problem
Current LPDDR5 protocol supports only 16 bits per channel, leading to suboptimal characterization and reduced signal integrity when multiple memory dies are connected in parallel, as they receive the same control signaling, degrading memory device performance.
Innovation Solution
Implementing a 64-bit channel controller with two 32-bit MCs and two 32-bit PHYs, coupled to memory dies via a multiplexed CS and CA bus configuration, allowing individual training of each memory die to improve signal integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple memory dies are connected in parallel to achieve 64-bit channel width, then the channel bandwidth is improved, but the signal integrity and training precision deteriorate because all dies receive the same control signaling
Solution Approach 1:
The patent segments the control signaling path by providing separate command-and-address (CA) bus inputs to each memory die. This allows individual training and control of each die rather than treating them as a single combined bus, thereby maintaining training precision while achieving high channel bandwidth through parallel configuration
Solution Approach 2:
The patent introduces separate CA bus intermediaries for each memory die between the channel controller and the dies. These dedicated control paths act as mediators that enable precise individual addressing and training of each die, preventing the signal integrity degradation that would occur with shared control signaling
2Measurement precision
If separate control signaling paths are provided for each memory die, then the training precision and signal integrity are improved, but the device complexity increases
Solution Approach 1:
The patent employs universal control signaling protocols and standardized bus interfaces for each memory die. By using the same LPDDR5 protocol and control structures across all dies, the system achieves individual die control without proportionally increasing complexity, as each die follows the same control paradigm
Solution Approach 2:
The patent merges the control architecture by using a unified channel controller that manages multiple dies through standardized interfaces. Rather than requiring separate controllers for each die, the system combines control functions in a single controller that can address and train each die individually through separate but standardized paths
3Productivity
If 64-bit channel width is implemented with current 16-bit per channel protocol, then more memory dies must be connected in parallel, but this increases the area occupied by the memory device
Solution Approach 1:
The patent transitions from a single-die architecture to a multi-die parallel architecture, adding the dimension of vertical stacking or side-by-side die arrangement. This allows the system to achieve 64-bit channel width by combining multiple 16-bit dies, effectively utilizing spatial dimensions to increase capacity without requiring a single excessively large die
Data Source
AI summary
This disclosure describes aspects of memory die interconnections to physical layer interfaces (PHYs) that may enable expanded channel bus width and improved signal integrity (SI). In aspects, a memory die is operably coupled to a first PHY via a command-and-address (CA) bus and data input/output (DQ) bus of the first PHY and to a second PHY via a chip select (CS) bus of the second PHY. The second PHY may provide a CS signal to the memory die, and the first PHY can perform a training procedure via CA signaling or DQ signaling. The training procedure may improve SI between the memory die and the PHYs. Additionally, a memory die may be interconnected to different PHYs to expand a channel bus width. Thus, by interconnecting memory dies to one or more PHYs as described herein, improved SI and expanded channel bus width can be achieved.