Configurable Memory Die Powerup Delay Circuit

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Solution Overview

Problem

Conventional memory systems experience high peak current demand during powerup operations due to simultaneous activation of all memory dies, leading to inefficient power supply usage and potential overheating issues as the number of memory dies and internal voltages increases.

Innovation Solution

Implementing powerup group detect circuitry to stagger the powerup sequence of memory dies across different time groups, reducing peak current demand by distributing the powerup operations over time, with each memory die assigned to a specific powerup group and delaying its subsystem activation based on assigned group timing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If all memory dies are activated simultaneously during powerup, then system functionality is established quickly, but peak current demand increases significantly

Engineering Contradiction:
Improvepowerup speedVSAvoidpeak current demand
Core Design Contradiction:
SpeedVSPower

Solution Approach 1:

The memory system divides all memory dies into multiple powerup groups (first powerup group and second powerup group). Dies in the first group are activated simultaneously at the initial powerup stage, while dies in the second group are activated subsequently at a later stage. This segmentation of the powerup process reduces peak current demand by distributing activation across time stages while maintaining relatively quick overall system startup.

Inventive Principle:
Principle #1Segmentation

2Quantity of substance

If the number of memory dies and internal voltages is increased, then memory capacity and performance improve, but peak current demand during powerup increases

Engineering Contradiction:
Improvememory capacityVSAvoidpeak current demand
Core Design Contradiction:
Quantity of substanceVSPower

Solution Approach 1:

The patent segments memory dies into multiple powerup groups based on their activation timing requirements. By organizing dies into first and second powerup groups with staggered activation, the system can accommodate a larger total number of memory dies and internal voltages without proportionally increasing peak current demand, as not all dies draw current simultaneously during powerup.

Inventive Principle:
Principle #1Segmentation

3Power

If powerup operations are staggered across different time groups, then peak current demand is reduced, but powerup sequence complexity increases

Engineering Contradiction:
Improvepeak current demandVSAvoidpowerup sequence complexity
Core Design Contradiction:
PowerVSDevice complexity

Solution Approach 1:

The patent implements preliminary action by pre-configuring powerup group assignments for different memory dies before powerup occurs. The controller is pre-programmed with knowledge of which dies belong to the first powerup group and which belong to the second powerup group. This preliminary organization allows the staggered powerup sequence to be executed automatically without requiring complex real-time control logic, thereby reducing powerup sequence complexity while still achieving peak current demand reduction.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11250890B2Memory with configurable die powerup delay
Publication Date: 2022.02.15 MICRON TECHNOLOGY INC
  • US11250890B2 patent drawing
  • US11250890B2 patent drawing
  • US11250890B2 patent drawing

AI summary

Memory devices and systems with configurable die powerup delay, and associated methods, are disclosed herein. In one embodiment, a memory system includes two or more memory dies. At least one memory die has a powerup group terminal and powerup group detect circuitry. The powerup group detect circuitry is configured to detect a powerup group assigned to the at least one memory die. The at least one memory die is configured to delay its powerup operation by a time delay corresponding to the powerup group to which it is assigned. In this manner, powerup operations of the two or more memory dies can be staggered to reduce peak current demand of the memory system.