3D Memory Die Numbering Circuits for Accurate Stack Identification
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Solution Overview
Problem
Existing three-dimensional integrated circuits (3DIC) face errors due to the need for manual programming of identification numbers on each memory die during fabrication, which increases the likelihood of misplacement and misidentification.
Innovation Solution
A memory system and die that automatically generate a number signal corresponding to the level in the 3DIC stack using a series of numbering circuits with sub-circuits that directly process bits of a previous stage number signal to produce a current stage number signal, reducing design complexity and ensuring accurate die placement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If identification numbers are programmed or set to each die through hardwires or e-fuses during fabrication, then each die can be correctly accessed in the 3DIC stack, but the complexity of the manufacturing process increases and the possibility of errors occurs
Solution Approach 1:
The patent implements self-service by enabling each memory die to automatically generate its own identification number through an on-die counter circuit. The counter circuit autonomously counts the number of memory dies in the stack and generates the corresponding identification number without requiring external programming or manual configuration during fabrication. This eliminates the need for hardwired or e-fuse based identification methods, thereby reducing manufacturing complexity while maintaining reliable die access.
2Manufacturing precision
If each die is labeled with identification number during fabrication, then die placement can be tracked, but the likelihood of error increases due to manual programming requirements
Solution Approach 1:
The patent eliminates manual programming errors by implementing self-service identification generation. Each memory die contains a counter circuit that automatically generates its identification number based on its position in the stack during the stacking process. This automated generation removes human intervention from the identification assignment process, thereby eliminating errors associated with manual programming while ensuring accurate die placement tracking.
Solution Approach 2:
The patent applies preliminary action by pre-configuring the counter circuit logic within each memory die before stacking. The counter circuit is designed in advance to automatically count and generate identification numbers during the stacking process, ensuring that each die receives the correct identification number without requiring post-fabrication programming or manual configuration.
3Loss of information
If identification numbers are programmed to each die, then die level information is available, but the process requires application to each die individually increasing complexity
Solution Approach 1:
The patent merges the identification generation function into the memory die itself by integrating a counter circuit within each die. This consolidation eliminates the need for separate external programming operations for each die. The counter circuit within each die automatically receives signals from adjacent dies and generates the appropriate identification number, thereby making level information available while reducing the complexity of individual die configuration processes.
Data Source
AI summary
Memory systems and memory dies are provided. The memory system of the present disclosure comprises a plurality of memory dies. The plurality of memory dies are stacked within the memory system. The plurality of memory dies respectively comprises a plurality of numbering circuits. The plurality of numbering circuits are coupled in series as a string. A current stage numbering circuit in the string comprises a plurality of sub-circuits. The plurality of sub-circuits are configured to respectively generate bits of a current stage number signal directly using bits of a previous stage number signal from a previous stage numbering circuit.