3D Memory Die Stacking Without Interposer Using Edge Cavities
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Solution Overview
Problem
Conventional semiconductor memory apparatuses require a large substrate wafer and an interposer to stack memory dies of the same kind, leading to increased size and manufacturing costs.
Innovation Solution
A method of stacking memory dies without using an interposer, involving the formation of cavities on the edge portions of memory dies to allow for under-fill material deposition and removal, enabling the stacking of multiple memory dies on a single wafer while avoiding the need for an interposer wafer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an interposer is used to stack memory dies, then the reliability of connections is improved, but the device size and manufacturing cost increase
Solution Approach 1:
The patent removes the interposer from the stacking structure, extracting the problematic component that caused increased device size and manufacturing cost while maintaining the essential function of connecting memory dies through alternative means (direct bonding and under-fill material)
Solution Approach 2:
The patent merges the functions of the interposer and under-fill material by allowing the under-fill material to serve both as structural support and as the medium for electrical connections between stacked memory dies, eliminating the need for a separate interposer layer
2Productivity
If a large substrate wafer is used to stack memory dies, then the stacking capability is achieved, but the wafer space utilization decreases
Solution Approach 1:
The patent transitions from a conventional 2D layout on large wafers to a 3D vertical stacking architecture, allowing multiple memory dies to be stacked in the vertical dimension without requiring proportionally larger wafer area, thereby improving space utilization
3Manufacturing precision
If edge portions of memory dies are removed to form cavities, then the under-fill material deposition is improved, but the memory die structure is modified
Solution Approach 1:
The patent performs preliminary modification of the memory die edge portions by removing material to form cavities before depositing the under-fill material, ensuring that the subsequent deposition process can properly accommodate and bond the under-fill material without defects
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the size of the semiconductor memory apparatus, lowers manufacturing costs, and allows for more efficient use of wafer space by enabling adjacent stacking of memory die stacks, thereby increasing production capacity.
Implementation Method 1
depositing an under-fill material on the wafer including the plurality of first memory dies formed thereon to form a first part of an under-fill layer
Data Source
AI summary
A method of manufacturing a semiconductor memory apparatus, in which a plurality of memory dies are stacked, includes forming first memory dies on a wafer. An under-fill material is deposited on a wafer, on which the first memory dies are formed, to form a first part of an under-fill layer. A first portion of the under-fill layer remaining on top surfaces of the first memory dies is removed by performing a half sawing process, and parts of edge portions of the first memory dies are removed during the removal of the first portion of the under-fill layer to form first cavities. Second memory dies are formed on the first memory dies. The under-fill material is deposited on the wafer including the second memory dies formed thereon to form a second part of the under-fill layer on a remaining part of the under-fill layer.