Memory Die Capacity Layout for Flexible TLC and QLC Scaling

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Solution Overview

Problem

Conventional semiconductor memory devices have binary data capacities, limiting their storage efficiency and flexibility, especially as technology advances and smaller form factors are required.

Innovation Solution

The development of memory dies with a non-binary data capacity of 683 Gb per memory block, allowing for operation in both TLC (three bits per cell) and QLC (four bits per cell) modes, enabling the formation of memory devices with binary capacities such as 256 GB, 512 GB, and 1 TB by combining multiple memory dies.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If memory devices use traditional binary capacity configuration, then manufacturing and addressing are simplified, but storage efficiency and flexibility are limited

Engineering Contradiction:
Improvestorage capacity flexibilityVSAvoidcapacity configuration complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent applies parameter changes by configuring memory dies with a specific non-binary capacity (683 Gb) that can be combined in different quantities to achieve various binary capacities. This allows the system to maintain flexibility in storage capacity while using standardized memory die units, resolving the contradiction between adaptability and complexity.

Inventive Principle:
Principle #35Parameter changes

2Quantity of substance

If array wafer size is reduced rapidly to improve technology, then storage density increases, but CMOS wafer size reduction lags behind creating integration challenges

Engineering Contradiction:
Improvestorage densityVSAvoidwafer integration complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent applies segmentation by dividing the memory device into multiple standardized memory dies, each with a specific capacity (683 Gb). This allows the array wafer to be scaled independently while maintaining standardized integration units, resolving the mismatch between rapid array wafer scaling and slower CMOS wafer scaling.

Inventive Principle:
Principle #1Segmentation

3Adaptability or versatility

If memory devices support multiple operating modes (TLC and QLC), then storage capacity options increase, but device configuration and control become more complex

Engineering Contradiction:
Improveoperating mode flexibilityVSAvoidmode configuration complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent applies universality by designing memory dies that can operate in multiple modes (TLC and QLC) with the same physical structure. The memory device supports both three bits per cell and four bits per cell operations, providing mode flexibility without requiring different hardware configurations, thus resolving the contradiction between versatility and complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS20240029789A1Memory die having a unique storage capacity
Publication Date: 2024.01.25 SANDISK TECHNOLOGIES LLC
  • US20240029789A1 patent drawing
  • US20240029789A1 patent drawing
  • US20240029789A1 patent drawing

AI summary

The memory die that includes a plurality of memory blocks. Each memory block includes a plurality of memory cells that are configured to store three bits of data in each memory cell when the memory die is in a TLC operating mode. The memory die has a non-binary data capacity, which is a multiple of 683 Gb, when the memory die is operating in the TLC operating mode.