Memory Die ZQ Calibration With Overlapped Pull-Up and Pull-Down
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor memory devices with shared ZQ terminals and external resistors experience increased processing time for impedance calibration as the number of memory dies increases, due to the need to adjust start timing for each die.
Innovation Solution
A control unit in each memory die executes pull-down calibration on one die while performing pull-up calibration on another, and vice versa, allowing simultaneous calibration operations across multiple dies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If ZQ calibration is performed sequentially for each memory die sharing a common external resistor, then calibration accuracy is maintained, but the processing time increases proportionally with the number of dies
Solution Approach 1:
The patent merges pull-up calibration of one memory die with pull-down calibration of another memory die by sharing the common external resistor. The control unit coordinates these operations so that both calibrations occur simultaneously, reducing total processing time from (N+1)t to approximately 2t while maintaining calibration accuracy for each die.
Solution Approach 2:
The patent implements continuous useful action by overlapping calibration operations. While one memory die undergoes pull-up calibration, another die simultaneously undergoes pull-down calibration, ensuring that the calibration process continues without idle periods and maximizing resource utilization of the shared external resistor.
2Device complexity
If multiple memory dies share ZQ terminals and external resistors to reduce manufacturing costs, then device complexity and cost decrease, but calibration time increases
Solution Approach 1:
The patent merges calibration operations across multiple memory dies that share common resources (ZQ terminals and external resistors). By coordinating pull-up and pull-down calibrations to occur simultaneously on different dies, the system maintains low device complexity while dramatically reducing calibration time.
Solution Approach 2:
The patent introduces dynamic control of calibration timing through the control unit, which adjusts the start timing and duration of calibration operations for each memory die. This dynamic approach allows flexible scheduling of overlapping calibrations, optimizing the balance between shared resource utilization and calibration speed.
3Measurement precision
If sequential calibration is performed for each memory die, then calibration precision is maintained, but productivity decreases
Solution Approach 1:
The patent combines multiple calibration operations into overlapping time windows, where pull-up calibration of one die and pull-down calibration of another die occur simultaneously. This merging of operations maintains individual calibration precision while increasing overall calibration throughput by processing multiple dies in parallel.
Solution Approach 2:
The control unit performs preliminary coordination of calibration schedules, determining optimal start times for each die's calibration based on shared resource availability. This preliminary planning enables seamless overlapping of calibration operations, maximizing productivity without compromising precision.
Data Source
AI summary
A semiconductor memory device and a control method thereof are provided. The semiconductor memory device includes a plurality of memory dies and a control unit. The memory dies are connected to a common external resistor through calibration pads. While executing pull-up calibration on the first memory die, the control unit is configured to execute pull-down calibration on at least one second memory die which is different from the first memory die. While executing pull-up calibration of the second memory die, the control unit is configured to execute pull-down calibration of the first memory die.