Memory Differential Input Calibration for Duty Cycle Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor memory systems face challenges in maintaining accurate clock signals due to duty cycle deviations, which can lead to incorrect operations and require additional test equipment for high-frequency signal generation, increasing costs and complexity.
Innovation Solution
A memory system incorporating a clock generation circuit that produces differential high-speed oscillation signals to test internal circuits and adjust duty cycles, reducing dependence on external test equipment and improving accuracy through Built-In Self Test (BIST) functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If external test equipment is used for high-frequency signal generation, then testing accuracy is improved, but device complexity and cost increase
Solution Approach 1:
The patent combines the test signal generation function with the memory device itself by integrating a clock generation circuit that produces differential high-speed oscillation signals. This merging eliminates the need for separate external test equipment, reducing device complexity while maintaining testing accuracy through built-in self-test capability.
Solution Approach 2:
The memory device performs self-testing by generating its own test signals through the integrated clock generation circuit. The device uses its internal resources to produce differential high-speed oscillation signals for testing internal circuits, eliminating dependence on external equipment and reducing overall system complexity.
2Measurement precision
If external test equipment is used for high-frequency signal generation, then testing capability is improved, but cost increases
Solution Approach 1:
The patent merges the test equipment functionality into the memory device by integrating a clock generation circuit that produces differential high-speed oscillation signals. This integration eliminates the need for separate external test equipment, reducing manufacturing cost while maintaining full testing capability through the built-in circuit.
Solution Approach 2:
The memory device provides its own testing capability through the integrated clock generation circuit, which generates high-frequency differential signals for internal circuit testing. This self-service approach eliminates the need for expensive external test equipment, reducing overall system cost while maintaining comprehensive testing capability.
3Reliability
If duty cycle deviation occurs in internal clock, then operation accuracy deteriorates, but additional control circuits increase complexity
Solution Approach 1:
The patent implements a feedback mechanism where the clock generation circuit continuously monitors and adjusts the duty cycle of internal clock signals. The circuit compares the actual duty cycle against a target value and dynamically adjusts timing parameters to maintain accuracy, ensuring reliable operation while managing control circuit complexity through efficient feedback control.
Solution Approach 2:
The clock generation circuit dynamically changes timing parameters to compensate for duty cycle deviations. By adjusting the phase and timing of clock signals based on detected deviations, the circuit maintains operation accuracy without requiring complex additional control structures, using parameter optimization instead of structural complexity.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
Embodiments of the disclosure provide a memory, which includes: a clock generation circuit, configured to generate a first oscillation signal and a second oscillation signal. The first oscillation signal and the second oscillation signal have a same frequency but opposite phases, and a duty cycle of the first oscillation signal and a duty cycle of the second oscillation signal are both within a first preset range. And the memory further includes a differential input circuit, which is configured to receive a first external signal and a second external signal, and generate a first internal signal and a second internal signal. Herein, the clock generation circuit is further configured to monitor at least one of the duty cycle of the first internal signal or the duty cycle of the second internal signal, and enable the at least one of the duty cycle of the first internal signal or the duty cycle of the second internal signal to be within a second preset range. According to the embodiments of the disclosure, the memory has a Duty Cycle Monitor (DCM) function and a Duty Cycle Adjust (DCA) function, and also can achieve detection and calibration on the differential input circuit.