3D Memory Cell Digit Line Layout for Lower Capacitive Coupling
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Solution Overview
Problem
The increased density of conductive interconnect structures in microelectronic devices poses challenges in forming adequate electrical communication with memory cells, particularly due to reduced spacing between neighboring conductive interconnects, which affects the formation and performance of memory arrays.
Innovation Solution
The implementation of vertically alternating high and low global digit lines, which reduces capacitive coupling between neighboring lines, allows for larger process margins and lower resistance, improving the operation of sense amplifiers and enabling better electrical communication with conductive pillar structures in microelectronic devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the spacing between neighboring conductive interconnect structures is reduced to increase memory cell density, then the density of memory cells increases, but the formation of adequate electrical communication with memory cells becomes difficult
Solution Approach 1:
The patent transitions from planar (2D) conductive interconnect structures to vertically stacked (3D) structures. Global digit lines are positioned at different vertical levels (first level above a first set of memory cells, second level above a second set of memory cells), allowing electrical communication without requiring reduced lateral spacing between interconnects. This dimensional change resolves the contradiction by maintaining adequate formation conditions while achieving high memory cell density.
2Quantity of substance
If conventional planar conductive interconnect structures are used with reduced spacing, then memory cell density increases, but capacitive coupling between neighboring lines increases
Solution Approach 1:
By stacking global digit lines at different vertical levels and separating them with insulating layers, the patent reduces parasitic capacitive coupling between adjacent conductive lines. The vertical separation combined with insulating materials between levels minimizes electric field interaction, thereby reducing capacitive coupling effects while maintaining high density through the third dimension.
Solution Approach 2:
Insulating layers are introduced as intermediary materials between the first and second global digit lines. These insulating layers act as mediators that electrically isolate the conductive lines at different levels, preventing direct capacitive coupling and reducing harmful electrical interference while allowing the dense vertical integration of memory cells.
3Quantity of substance
If more conductive pillar structures are coupled with global digit lines to increase memory density, then the number of sense amplifiers must increase, but device complexity increases
Solution Approach 1:
Each global digit line structure is designed to serve multiple memory cell decks simultaneously. The first global digit line couples with a first set of memory cells at a first vertical level, while the second global digit line couples with a second set of memory cells at a second vertical level. This multi-functional design allows a single global digit line to service multiple memory arrays, reducing the total number of sense amplifiers needed compared to dedicated lines for each memory deck.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the formation and operation of microelectronic devices by reducing resistance-capacitance (RC) delay, allowing for a greater quantity of conductive pillar structures to be coupled with global digit lines and decreasing the number of sense amplifiers, thereby improving the overall performance and density of memory arrays.
Implementation Method 1
vertically alternating high and low global digit lines, which reduces capacitive coupling between neighboring lines
Data Source
AI summary
A microelectronic device comprises a vertical stack of memory cells. Each vertical stack of memory cells comprises a vertical stack of access devices, a vertical stack of capacitors horizontally neighboring the vertical stack of access devices, and a conductive pillar structure in electrical communication with the vertical stack of access devices. The microelectronic device further comprises first global digit lines vertically neighboring the vertical stacks of memory cells, and second global digit lines horizontally interleaved with the first global digit lines in a horizontal direction, the second global digit lines vertically spaced from the vertical stacks of memory cells a greater distance than the first global digit lines. Related memory devices, electronic systems, and methods are also described.