Integrated Memory Assembly Digit-Line Segmentation
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Solution Overview
Problem
Conventional memory architectures have high time constants associated with individual digit-lines, which affect performance in reading and writing operations due to the number of memory cells, capacitance, and resistance along the digit-line.
Innovation Solution
The implementation of vertically stacked memory arrays with digit-line configurations that couple inner points of digit-lines to sense-amplifier circuitry, reducing the total time constant and improving timing performance by optimizing the placement of sense-amplifier and wordline driver circuitry under the memory arrays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If conventional open bitline architecture with sense amplifiers at ends of digit-lines is used, then memory arrays can be laid out simply, but the time constant associated with individual digit-lines becomes large
Solution Approach 1:
The patent segments the digit-line into multiple sections by introducing intermediate connection points that couple to sense-amplifier circuitry at inner points along the digit-line, rather than only at the ends. This segmentation divides the long digit-line into shorter effective segments, reducing the time constant associated with each segment while maintaining the overall memory array functionality.
2Quantity of substance
If more memory cells are placed along the digit-line to increase capacity, then storage density improves, but the time constant increases due to more cells, capacitance, and resistance
Solution Approach 1:
The patent transitions from a two-dimensional layout to a three-dimensional vertically-stacked architecture where memory arrays are stacked in multiple tiers along the digit-line. This allows memory cells to be arranged in vertical columns rather than only horizontal rows, increasing the number of memory cells per digit-line while reducing the horizontal distance and resistance, thereby managing the time constant despite increased cell count.
3Ease of operation
If sense-amplifier circuitry is placed at ends of digit-lines, then circuit layout is simplified, but timing performance deteriorates
Solution Approach 1:
The patent applies local quality by placing sense-amplifier circuitry at specific inner points along the digit-line rather than uniformly at the ends. This localized placement optimizes the timing performance for specific segments of the memory array while maintaining reasonable layout complexity, as each sense amplifier serves a localized region with reduced time constant.
4Area of stationary object
If memory arrays are packed more tightly to conserve semiconductor real estate, then area efficiency improves, but the complexity of interconnect and routing increases
Solution Approach 1:
The patent utilizes vertical stacking to arrange memory arrays in multiple tiers, allowing tighter packing in the horizontal plane while routing interconnects vertically between tiers. This three-dimensional arrangement conserves semiconductor real estate by increasing storage density without proportionally increasing the footprint, while the vertical interconnect routing manages complexity through standardized stacking patterns.
Data Source
AI summary
Some embodiments include an integrated assembly having a second deck over a first deck. A true digit-line has a short first region along the first deck and a long second region along the second deck. A complementary digit-line has a long first region along the first deck and a short second region along the second deck. A first set of first memory cells is associated with the true digit-line. The first set includes a first subset along the short first region, a second subset along a portion of the long second region, and a third subset along another portion of the long second region. A routing region of the true digit-line extends between the second and third subsets of the first memory cells. A connection extends from the short first region to the routing region of the true digit-line.