Nonvolatile Memory Cell Diode Capacitance for Erase Stability
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Solution Overview
Problem
In nonvolatile semiconductor memory devices using variable resistance elements, erroneous writing can occur during data erase operations due to voltage fluctuations when the variable resistance element shifts from a low to a high resistance state, causing the applied voltage to exceed the write voltage and leading to unintended data changes.
Innovation Solution
The nonvolatile semiconductor memory device applies an erasing pulse in the reverse bias direction to the diode, allowing it to function as a capacitor, which charges or discharges, thereby applying a stable voltage to the variable resistance element, preventing voltage spikes and erroneous writing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a forward bias voltage is applied to the diode during data erase operation, then the variable resistance element can be switched from low resistance state to high resistance state, but the voltage applied to the variable resistance element may rise and exceed the writing voltage causing erroneous writing
Solution Approach 1:
A capacitor is introduced as an intermediary component connected in parallel with the variable resistance element. This capacitor absorbs voltage spikes that occur during the erase operation, preventing the voltage from exceeding the writing threshold and causing erroneous writing. The capacitor acts as a buffer between the diode and the variable resistance element, mediating the voltage fluctuations.
Solution Approach 2:
The capacitor is pre-charged to a specific voltage level before the erase operation begins. This beforehand cushioning of electrical charge provides a reserve that absorbs the voltage surge when the variable resistance element switches states, preventing the harmful voltage spike from reaching the variable resistance element.
2Productivity
If the variable resistance element is used to store data, then memory cell stacking to three-dimensional structure is enabled for higher integration, but voltage control during erase operations becomes difficult
Solution Approach 1:
The capacitor serves as a voltage control intermediary that simplifies the complex voltage management required in three-dimensional stacked memory cells. By placing the capacitor in parallel with each variable resistance element, the system gains local voltage control capability without requiring complex global control circuits, thus managing the complexity inherent in high-density stacking.
Solution Approach 2:
The memory structure is segmented into multiple stacked layers, with each memory cell independently controlled by its own capacitor. This segmentation allows parallel operation of multiple memory cells across different voltage levels, managing the complexity of voltage control in three-dimensional structures by dividing the system into independent, manageable units.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively suppresses the risk of erroneous writing by maintaining a consistent voltage during data erase operations, ensuring accurate data storage and reducing the risk of unintended changes in the memory cells.
Implementation Method 1
applies an erasing pulse in the reverse bias direction to the diode, allowing it to function as a capacitor, which charges or discharges, thereby applying a stable voltage to the variable resistance element
Implementation Method 2
a certain voltage lower than the voltage applied in the writing operation is applied for a long time to the variable resistance element which is in a low resistance state, in order to cause Joule heat by a current flowing through the variable resistance element
Data Source
AI summary
According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control circuit. The memory cell array includes a plurality of first wirings, a plurality of second wirings intersecting the plurality of first wirings, and a plurality of memory cells provided at the intersections of the plurality of first and second wirings and each including a non-ohmic element and a variable resistance element connected in series. The control circuit selects one of the plurality of memory cells, generates an erasing pulse for erasing data from the selected memory cell, and supplies the erasing pulse to the selected memory cell. The control circuit executes data erase by applying a voltage of the erasing pulse to the non-ohmic element in the reverse bias direction.