Semiconductor Memory Erase Circuit Diode Area Reduction
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Solution Overview
Problem
Current semiconductor memory technologies face challenges in efficiently reducing the chip size and manufacturing costs while maintaining performance, particularly in the design and layout of erase circuits for NAND flash memory, where the area required for transferring erase voltage is substantial.
Innovation Solution
The implementation of a diode circuit in the erase circuit, which applies the erase voltage to the bit lines, reducing the area needed compared to using high breakdown voltage transistors, and in the second embodiment, using field-effect transistors connected to alternate bit lines to achieve capacitive coupling for voltage transfer during erase operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high breakdown voltage transistors are used to transfer erase voltage to bit lines, then the erase operation can be performed reliably, but the chip area increases and manufacturing cost increases
Solution Approach 1:
The patent introduces an intermediary capacitor coupled between the bit line and the erase voltage source. This capacitor acts as a mediator that transfers the erase voltage to the bit line without requiring high breakdown voltage transistors directly on the chip, thus reducing chip area while maintaining erase operation reliability
Solution Approach 2:
The patent moves the high breakdown voltage transistor from the two-dimensional chip plane to an external component (off-chip), utilizing the third dimension (spatial relocation) to resolve the area constraint while preserving the functional requirement for high voltage generation
2Reliability
If high breakdown voltage transistors are used to transfer erase voltage, then erase voltage can be applied to bit lines, but the manufacturing cost increases
Solution Approach 1:
The capacitor serves as an intermediary that enables erase voltage transfer through simpler, lower-cost circuitry. By using a capacitor instead of high breakdown voltage transistors, the manufacturing process becomes less complex and more cost-effective while achieving the same functional outcome
Solution Approach 2:
The patent replaces expensive, complex high breakdown voltage transistors with a simpler capacitor-based solution that is cheaper to manufacture. The external high voltage generator, while simple in structure, provides the necessary function at lower manufacturing cost
3Area of stationary object
If diode circuit is used instead of high breakdown voltage transistors, then chip area is reduced, but design flexibility may be limited
Solution Approach 1:
The capacitor-based erase circuit is designed to be universally applicable across different memory architectures and configurations. The same basic principle can be adapted to various bit line arrangements, memory cell types, and integration schemes, maintaining design flexibility while reducing area
Solution Approach 2:
The patent employs dynamic control of the capacitor charging and discharging cycles to achieve erase operations. This dynamic approach allows flexible timing control and can be adapted to different operational requirements, maintaining versatility despite the simplified hardware structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for a reduction in chip size and manufacturing costs by minimizing the area of high breakdown voltage transistor regions and improving design flexibility, thereby enhancing manufacturing yield and reducing operational errors during erase, read, and write operations.
Implementation Method 1
using field-effect transistors connected to alternate bit lines to achieve capacitive coupling for voltage transfer during erase operations
Data Source
AI summary
According to one embodiment, a semiconductor memory includes: a first bit line; a first select transistor having a first terminal connected to the first bit line; a first memory cell connected to a second terminal of the first select transistor; a circuit connected to the first bit line and applying an erase voltage to be applied to the first memory cell to the bit line via the first terminal and the second terminal; and a diode connected to the first bit line and the first circuit.