Memory Device Direct Test Access via Isolation Pin
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Solution Overview
Problem
Non-volatile memory devices, such as eMMC and UFS, require direct accessibility for testing, but existing methods involve indirect access through a memory controller, complicating the testing process and increasing testing time.
Innovation Solution
A memory device architecture with a package substrate that includes isolation, test mode select, test clock, and test data pins allows direct access to memory dies for testing, enabling isolation from the controller and simultaneous testing of multiple memory units using a limited number of test pins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If indirect access through memory controller is used for testing, then memory device can be tested, but testing process becomes complicated and testing time increases
Solution Approach 1:
The patent segments the testing function by introducing a dedicated test mode that separates testing operations from normal controller-mediated operations. The memory device is divided into normal operation mode (through controller) and test mode (direct access), allowing simplified testing without affecting normal device functionality.
Solution Approach 2:
The patent introduces a test mode select pin as an intermediary mechanism that switches between controller-mediated access and direct test access. This intermediary allows the system to bypass the memory controller during testing without permanently altering the device architecture or normal operation.
2Loss of time
If direct access to memory dies is implemented for testing, then testing time decreases, but number of test pins increases
Solution Approach 1:
The test mode select pin serves multiple functions: it enables direct test access, isolates the memory die from the controller, and activates test-specific signal paths. This multi-functional pin reduces the need for separate dedicated pins for each testing function, thereby minimizing the overall pin count while enabling comprehensive direct access testing.
Solution Approach 2:
The patent merges the test control functions into the existing package substrate architecture by integrating test pins with the memory device package. The test mode select pin, test clock pin, and test data pin are combined into a unified test interface that shares the package substrate, reducing the total number of required pins compared to separate testing interfaces.
3Ease of operation
If memory units are accessed indirectly via memory controller, then normal operation is maintained, but testing efficiency decreases
Solution Approach 1:
The patent implements a dynamic switching mechanism where the memory device can operate in normal mode (through controller) or test mode (direct access) based on the state of the test mode select pin. This dynamic capability allows the system to optimize for either normal operation or testing efficiency depending on the operational context, without compromising either function.
Data Source
AI summary
A memory device includes a plurality of pins, a controller die coupled to the isolation pin, and a memory die. The plurality of pins include an isolation pin, a test mode select pin configured to switch an operation mode of the memory die, a test clock pin configured to receive a test clock, and a test data pin configured to perform a data transmission. The controller die is coupled to the isolation pin. The memory die is coupled to the test mode select pin, the test clock pin, and the test data pin.