Memory Disabling Circuit Fuse Tri-State Isolation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor memory chips with defective dies (NG parts) can inadvertently be packaged due to variations in testing hardware, environment, and items, leading to yield and cost issues despite final testing filters.
Innovation Solution
A disabling circuit with a fuse is integrated into the memory, which generates a tri-state (high impedance) output when activated, preventing access to defective memory units and ensuring they are identified as NG parts during subsequent processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wafer testing is performed with multiple test patterns and final testing with tighter parameters, then the quality of memory products is improved, but defective dies may still be mistakenly packaged due to testing variations
Solution Approach 1:
The patent applies preliminary action by implementing a disabling circuit with a fuse that is activated during wafer testing to permanently disable defective dies. This preliminary disabling action ensures that even if testing variations cause NG parts to pass, they are immediately identified and disabled, preventing them from being packaged as good products.
Solution Approach 2:
The disabling circuit acts as an intermediary between the testing system and the packaging system. It receives test results and implements a permanent disable state through the fuse, serving as a mediator that ensures defective dies are reliably identified and isolated regardless of testing variations.
2Reliability
If NG parts are filtered out by final test, then product quality is maintained, but packaging yield and testing efficiency are reduced due to re-testing and verification requirements
Solution Approach 1:
The disabling circuit performs preliminary action by permanently disabling defective dies during the wafer testing stage itself, rather than relying solely on final testing. This eliminates the need for re-testing and verification during packaging, as the disabling state is already established, thereby improving both productivity and reliability.
3Reliability
If a disabling circuit with fuse is integrated into the memory, then defective dies are immediately identified and isolated, but device complexity increases
Solution Approach 1:
The disabling circuit extracts the defect identification and isolation function from the main memory operation. By separating this function into a dedicated circuit with a fuse, the patent achieves reliable defective die identification while minimizing the impact on the core memory structure and operation.
Solution Approach 2:
The disabling circuit applies local quality by implementing the disable function only at the specific location of defective dies through the fuse. This localized approach allows individual defective dies to be disabled without affecting the operation of good dies, maintaining overall memory functionality while improving reliability.
Data Source
AI summary
A memory with disabling circuit includes a memory matrix and a disabling circuit. The memory matrix includes a data input/output end and an output enable end. The disabling circuit includes a fuse and an output end. When the fuse is not blown, the disabling circuit transmits the signal of the data input/output end to the output end according to the signal of the output enable end. When the fuse is blown, the disabling circuit generates a tri-state to the output end. Therefore, external circuits cannot perform actions of reading or writing to access the memory matrix.