Memory Power-Line Discharge Delay for Safe Cache Flush

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Solution Overview

Problem

Existing information processing apparatuses face data loss during power failures or instantaneous interruptions due to incomplete cache flush operations, as the discharge circuit may discharge power before the cache flush is finished, requiring backup power supplies and periodic management.

Innovation Solution

Incorporating a delay circuit that postpones the discharge of the power supply line charge for a predetermined period after detecting a power voltage drop, allowing sufficient time for the cache flush operation to complete using the remaining charge.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If the discharge circuit discharges charges immediately upon detecting a power voltage drop, then the power failure response is fast, but the cache flush operation may be interrupted causing data loss

Engineering Contradiction:
Improvepower failure response speedVSAvoiddata integrity
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The delay circuit performs preliminary action by postponing the discharge operation for a predetermined period after detecting a power voltage drop. This allows the cache flush operation to complete first, ensuring data integrity before discharging the power supply line charges. The delay circuit proactively manages the timing sequence to prevent data loss while maintaining responsive power failure handling.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If a backup power supply is used to secure cache flush time, then data integrity is maintained, but device complexity and management overhead increase

Engineering Contradiction:
Improvedata integrityVSAvoidpower supply system complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The invention extracts the timing control function from the complex backup power supply system and implements it through a simple delay circuit. Instead of using a backup power supply with switching circuits and periodic management operations, the solution removes the need for these complex components by simply delaying the discharge operation for a predetermined period, achieving the same data protection goal with much simpler hardware.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The delay circuit uses a simple, inexpensive timing mechanism rather than a complex backup power supply system. The predetermined period delay is achieved through basic electronic timing components that are much cheaper and simpler than battery backup systems, switching circuits, and periodic management infrastructure, while still providing adequate time for cache flush completion.

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

3Productivity

If the discharge circuit operates immediately upon power failure, then power is quickly removed, but remaining cache data is lost

Engineering Contradiction:
Improvepower off efficiencyVSAvoidcache data loss
Core Design Contradiction:
ProductivityVSLoss of information

Solution Approach 1:

The delay circuit performs preliminary action by delaying the discharge operation to allow cache flush to complete first. This preliminary timing adjustment ensures that data is safely transferred from cache to storage before the power supply line charges are discharged, preventing information loss while maintaining efficient power off operation.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution ensures the cache flush operation is completed even during power instability, eliminating the need for backup power supplies and periodic management, thereby preventing data loss and enhancing system reliability.

Implementation Method 1

a delay circuit configured to delay receipt of a control signal by the discharge circuit for a predetermined period after the discharge circuit receives a charge discharge instruction from the memory control unit

Methodology Applied
Scientific EffectCapacitance: Capacitance

Implementation Method 2

a detection circuit configured to detect a drop in the power supply voltage

Methodology Applied
Scientific EffectVoltage detection:

Data Source

PatentUS11294445B2Information processing apparatus and method of controlling information processing apparatus
Publication Date: 2022.04.05 CANON KK
  • US11294445B2 patent drawing
  • US11294445B2 patent drawing
  • US11294445B2 patent drawing

AI summary

An information processing apparatus includes a memory, a control unit to accept an access to the memory, a power supply circuit to supply a voltage to the memory and the control unit, a detection circuit to detect a drop in the voltage, a discharge circuit, and a delay circuit. The discharge circuit discharges a charge on a voltage supply line extending between the power supply circuit and the memory. The delay circuit delays receipt of a control signal by the discharge circuit for a predetermined period after the discharge circuit receives a charge discharge instruction from the control unit. The control signal is to control discharging the supply line charge. The discharge circuit discharges supply line charges per a control signal based on detection of a drop in the voltage by the detection circuit and based on the delay of the control signal delayed by the delay circuit.