3D Memory Device Discharge Sequence for Reliability
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Solution Overview
Problem
Current memory devices face challenges in improving the reliability of verify and read operations, particularly in three-dimensionally structured memory devices, where the integration density is limited and operational efficiency is hindered by complex voltage management and discharge sequences.
Innovation Solution
A memory device and method that include a first and second select line, word lines coupled to memory cells, and peripheral circuits that supply turn-on, verify, and pass voltages, with control logic to equalize potentials and sequentially discharge word lines during verify and read operations, ensuring reliable program and read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensionally structured memory devices are used to overcome limited integration density, then integration density is improved, but operational reliability deteriorates due to complex voltage management and discharge sequences
Solution Approach 1:
The patent segments the discharge operation into two distinct phases: a first discharge phase where the first select line is discharged while the second select line remains charged, and a second discharge phase where the second select line is discharged. This segmentation allows independent control of discharge sequences for different select lines, enabling reliable voltage management in three-dimensional memory structures without compromising integration density.
Solution Approach 2:
The patent applies preliminary action by performing the first discharge phase before the second discharge phase. The first select line is discharged in advance while the second select line remains charged, preparing the memory device for subsequent operations. This preliminary discharge sequence ensures that voltage potentials are properly managed before completing the full discharge, thereby improving operational reliability in high-density three-dimensional memory devices.
2Measurement precision
If complex voltage management is implemented to ensure accurate verification and reading, then data integrity is improved, but device complexity increases
Solution Approach 1:
The patent segments the voltage management process into distinct phases corresponding to different discharge sequences. By dividing the discharge operation into a first discharge phase for the first select line and a second discharge phase for the second select line, the complex voltage management is broken down into manageable, independently controllable stages. This segmentation maintains verification accuracy while reducing the perceived complexity of voltage management.
Solution Approach 2:
The patent implements preliminary action by establishing specific voltage potentials on select lines before verification operations. The first select line is discharged in advance while the second select line remains charged, creating a controlled voltage environment that simplifies subsequent verification and read operations. This preliminary voltage setup ensures measurement precision without requiring complex real-time voltage management during verification.
3Reliability
If sequential discharge of word lines is performed to improve reliability, then operational stability is improved, but operation time increases
Solution Approach 1:
The patent segments the discharge operation into parallelizable phases where the first select line discharge and second select line discharge occur in sequence but can be optimized independently. This segmentation allows for efficient timing control where each discharge phase is executed promptly, minimizing the total operation time while maintaining the reliability benefits of sequential discharge for different select lines.
Data Source
AI summary
A memory device includes a memory block coupled to a plurality of word lines arranged in parallel with each other between a first select line and a second select line. Further included are peripheral circuits supplying a verify voltage and a pass voltage to the first select line, the second select line, and the word lines, selectively discharging the first select line, the second select line and the word lines, and verifying memory cells coupled to a selected word line of the word lines. Also, included is a control logic controlling the peripheral circuits so that potentials of the selected word line, unselected word lines and the first and second select lines are the same as each other after verifying the memory cells and the first and second select lines are discharged after discharging the selected and unselected word lines, and an operating method thereof.