Non-Volatile Memory Programming Speed via Discharge Transistor Segmentation
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Solution Overview
Problem
The existing non-volatile memory device architecture, particularly in Flash-Nor type, faces inefficiencies in programming speed due to high discharge times, which affect the overall performance and speed of data storage and manipulation in multimedia applications.
Innovation Solution
The introduction of a decoder that generates specific select signals to enable global and local bit-lines, combined with discharge transistors controlled by complementary signals, allows for simultaneous discharge of one bit-line while programming another, reducing idle time and enhancing programming speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a decoder generates select signals to enable global and local bit-lines sequentially, then programming can be performed on selected cells, but discharge times become a bottleneck that reduces programming speed
Solution Approach 1:
The patent applies preliminary action by enabling the discharge transistor before the programming pulse is applied to the selected cell. The discharge transistor is activated in advance to prepare the bit-line for rapid discharge after programming, reducing the overall discharge time that previously bottlenecked programming speed. This preliminary preparation allows the system to quickly transition between programming operations on different cells.
Solution Approach 2:
The patent achieves continuity of useful action by overlapping the discharge phase of one cell with the programming phase of the next cell. While one bit-line is being discharged, another bit-line can simultaneously undergo programming. This eliminates idle time between programming operations and maintains continuous productive activity across multiple bit-lines, effectively masking the discharge time penalty.
2Speed
If discharge transistors are added to each global bit-line, then discharge time is reduced and programming speed improves, but device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the bit-line discharge function into separate dedicated discharge transistors for each global bit-line. Instead of using a shared or complex timing mechanism to control discharge, each bit-line has its own independently controlled discharge transistor. This segmentation simplifies the control logic while enabling parallel discharge operations across multiple bit-lines, improving programming speed despite the increase in transistor count.
Data Source
AI summary
A device with non volatile memory cells, with optimized programming, of the type comprising a sector of matrix memory cells organized in rows and columns, with the columns organized in a plurality of global bit-lines associated with at least one plurality of local bit-lines and respectively enabled by a first select signal and by at least one second select signal generated by a decoder, these columns being associated with at least one program load PL controlled by a logic circuit and suitable for applying a programming pulse to a plurality of cells belonging to the enabled bit-lines, comprising a plurality of discharge transistors, each associated with a corresponding column controlled by a control signal complementary to the control signal of the adjacent discharge transistor.