Memory Dispatcher Lockstep Verification for ASIL-D
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Solution Overview
Problem
The automotive industry faces a challenge in meeting the highest automotive Safety Integrity Level (ASIL-D) requirements for external memory used in autonomous driving systems, as existing consumer-grade external Dynamic Random Access Memory (DRAM) only meets ASIL-B integrity levels, which is insufficient for life-threatening scenarios.
Innovation Solution
A memory dispatcher system that operates in lockstep mode for high integrity levels (ASIL-D) by duplicating data and addresses without processing unit intervention, and in full performance mode for lower integrity levels (ASIL-B) without replication, ensuring data integrity and performance according to ISO 26262 standards.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If external memory is used to increase storage capacity, then storage capacity is improved, but data integrity level deteriorates (ASIL-B vs ASIL-D)
Solution Approach 1:
The patent implements lockstep mode where data is copied to both internal memory and external memory simultaneously. The internal memory serves as a reference copy to verify the integrity of external memory data, enabling ASIL-D compliance while utilizing ASIL-B external memory for storage capacity.
Solution Approach 2:
The patent introduces an intermediary verification mechanism where internal memory acts as a mediator to validate external memory data. This intermediary layer allows the system to use external memory while maintaining ASIL-D integrity through continuous verification against the internal memory reference.
2Reliability
If lockstep mode is used for high integrity level, then data integrity is improved, but computation performance deteriorates
Solution Approach 1:
The patent dynamically switches between lockstep mode and full performance mode based on the required integrity level of the current operation. This dynamic adaptation allows the system to optimize performance by using full performance mode for non-critical operations while maintaining lockstep mode only when ASIL-D integrity is required.
Solution Approach 2:
The patent applies different operational modes to different memory access patterns and data types. Critical safety-related data accesses use lockstep mode for high integrity, while non-critical accesses use full performance mode, creating local quality variations optimized for different functional requirements.
3Measurement precision
If data replication is performed, then diagnostic coverage is improved, but device complexity deteriorates
Solution Approach 1:
The patent makes the memory system multi-functional by implementing a unified memory interface that handles both lockstep and full performance modes through the same hardware infrastructure. This universality allows data replication and verification without requiring separate dedicated hardware paths, reducing overall system complexity.
Data Source
AI summary
A memory dispatcher, including an address decoder configured to decode a write address of received write data; a lockstep processor configured to generate, based on the decoded write address, primary and redundant memory write addresses and corresponding primary and redundant copies of the write data, if the decoded write address corresponds with a lockstep region of the memory; and a comparator coupled to the lockstep processor, and configured to compare the primary and redundant copies of the write data, and to compare the primary and redundant memory write addresses.