Non-volatile Memory Disturb Suppression via Segmented Power Supply
Solution Overview
Problem
Conventional non-volatile semiconductor memory devices experience disturbance during data writing, leading to variations in the charge storage state of memory cells, particularly in EEPROMs with small rewriting units, due to unintended charge injection into non-selected memory cells, which can result in data loss over repeated operations.
Innovation Solution
A non-volatile semiconductor memory device with a matrix of word lines, memory cells connected to bit lines, and power supply units with switching mechanisms that apply charge storage gate or inhibition gate voltages based on the presence of a selected memory cell, allowing for independent voltage control of each word line to prevent disturbance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If common word lines are used for both selected and non-selected bytes, then device complexity is reduced, but disturbance occurs in non-selected memory cells due to unintended charge injection
Solution Approach 1:
The word line structure is segmented into selected byte word lines and non-selected byte word lines, with separate power supply units for each segment. This allows independent voltage control to prevent charge injection into non-selected memory cells while maintaining a unified overall structure.
Solution Approach 2:
Different voltage characteristics are applied to different regions: selected byte word lines receive high voltage for charge injection, while non-selected byte word lines are held at low voltage to prevent disturbance. This local differentiation resolves the contradiction between structure simplicity and reliability.
2Reliability
If independent row-direction address decoders are provided for each byte, then disturbance is suppressed, but device complexity and area increase
Solution Approach 1:
Multiple address decoders are merged into a single shared address decoder that controls all bytes. This shared decoder works in conjunction with separate power supply units to achieve disturbance suppression without replicating decoder circuits for each byte.
Solution Approach 2:
Power supply units act as intermediaries between the shared address decoder and the memory cells. They translate the decoder's output into appropriate voltage levels for selected and non-selected word lines, enabling reliable operation without independent decoders.
3Productivity
If high voltage is applied to word lines for data writing, then writing speed is improved, but unintended charge injection into non-selected cells causes disturbance
Solution Approach 1:
The power supply system is segmented into separate units for selected and non-selected byte word lines. This allows the selected word lines to receive high voltage for fast writing while non-selected word lines are maintained at low voltage to prevent disturbance.
Solution Approach 2:
High voltage is applied locally only to selected word lines during writing operations, while non-selected word lines maintain low voltage. This localized voltage application enables high-speed writing without causing charge injection into non-selected memory cells.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively suppresses disturbance in non-selected memory cells by allowing for precise control of voltages applied to word lines, ensuring data integrity and preventing data loss, while also enabling miniaturization without the need for independent row-direction address decoders.
Implementation Method 1
a non-volatile semiconductor memory device that writes data by storing a charge in a charge storage layer in a memory cell by a quantum tunnel effect
Data Source
Figure 1
Figure 2
Figure 3
AI summary
Proposed is a non-volatile semiconductor storage device with which, while effecting miniaturization, it is possible to suppress a disturb occurrence better than before. In a non-volatile semiconductor storage device, forming a plurality of words in a matrix, disposing a power source unit for each word line column (memory well), imparting a different unit voltage to each power source unit corresponding to whether a selected memory well is present in a given word line column, switching on a word line unit basis a switch mechanism of each power source unit according to a control line voltage value, and individually imparting to each word line either a charge storage gate voltage or a charge storage interdiction gate voltage, it is possible to freely set for each word line column a charge storage interdiction gate voltage value or a bit line voltage value which is capable of suppressing a disturb occurrence. A plurality of power source units are connected to a common control line in the row direction, obviating the need for a separate address decoder for each word column line, and allowing effecting miniaturization.