Semiconductor Memory Disturbance Prevention via Hierarchical Biasing
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Solution Overview
Problem
Next-generation semiconductor memory apparatuses face challenges in maintaining data integrity due to disturbances caused by adjacent memory cells turning on unintentionally, leading to data loss, especially when voltage levels of unselected bit and word lines are not properly managed.
Innovation Solution
The semiconductor memory apparatus employs a hierarchical bit line and word line structure with a bit line control circuit and word line control circuit to apply specific bias voltages to selected and unselected bit and word lines, including multiple voltage levels to minimize the probability of adjacent memory cells being turned on, thereby reducing disturbances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If voltage levels of unselected bit and word lines are not properly managed, then device complexity is reduced, but data integrity deteriorates due to disturbances from adjacent memory cells turning on unintentionally
Solution Approach 1:
The patent applies different voltage levels to different groups of unselected bit lines and word lines based on their proximity to the selected line. Specifically, unselected lines adjacent to the selected line receive a first voltage level, while unselected lines not adjacent receive a second voltage level. This localized differentiation prevents disturbances in adjacent memory cells while maintaining data integrity, resolving the contradiction between reliability and complexity by making voltage management adaptive rather than uniform.
Solution Approach 2:
The patent changes the voltage parameter of unselected bit lines and word lines based on their position relative to the selected line. By applying a first voltage level to adjacent unselected lines and a second voltage level to non-adjacent unselected lines, the system dynamically adjusts voltage parameters to prevent unintended activation of adjacent memory cells, thereby ensuring data integrity without requiring overly complex management mechanisms.
2Reliability
If multiple voltage levels are applied to unselected bit and word lines to prevent adjacent memory cell activation, then data integrity is improved, but device complexity increases
Solution Approach 1:
The patent segments unselected bit lines and word lines into two groups: those adjacent to the selected line and those not adjacent. Each group is assigned a different voltage level (first voltage level for adjacent, second voltage level for non-adjacent). This segmentation allows the control circuit to manage voltage levels in a structured manner, improving data integrity while keeping the control complexity manageable through clear grouping rather than individual control of each line.
Solution Approach 2:
The patent implements local quality by applying different voltage characteristics to different spatial regions of the bit line and word line arrays. Adjacent unselected lines receive a first voltage level to prevent disturbance, while non-adjacent lines receive a second voltage level. This localized approach ensures data integrity is improved where needed (near selected lines) without unnecessarily complicating the control of distant lines.
3Device complexity
If a single voltage level is applied to all unselected bit and word lines, then device complexity is minimized, but disturbances occur causing adjacent memory cells to turn on unintentionally
Solution Approach 1:
The patent addresses the harmful effect of disturbances by applying different voltage levels to unselected lines based on their proximity to the selected line. Adjacent unselected lines receive a first voltage level that prevents unintended activation, while non-adjacent lines receive a second voltage level. This local differentiation eliminates disturbances in critical areas without requiring complex individual control of every line, thus reducing harmful effects while maintaining reasonable simplicity.
Solution Approach 2:
The patent changes the voltage parameter of unselected bit lines and word lines based on their position relative to the selected line. By applying a first voltage level to adjacent unselected lines and a second voltage level to non-adjacent unselected lines, the system dynamically adjusts voltage parameters to prevent unintended activation of adjacent memory cells, thereby ensuring data integrity without requiring overly complex management mechanisms.
Data Source
AI summary
A semiconductor memory apparatus includes an access line control circuit. The access line control circuit applies a selected bias voltage to a selected access line coupled with a target memory cell and applies a first unselected bias voltage to an unselected access line adjacent to the selected access line. A second unselected bias voltage is applied to an unselected access line not adjacent to the selected access line.