Memory Row Disturbance Monitoring With Partial Bit-Width Comparison
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Solution Overview
Problem
Existing memory devices face issues with usage-based disturbance due to electromagnetic coupling between adjacent memory cells, leading to voltage fluctuations and data corruption, which are inefficiently monitored using full bit-width comparisons that consume power and resources.
Innovation Solution
Implementing a power-efficient monitoring system that foregoes frequent updates of worse-case conditions until a substantially worse condition is detected and uses partial bit-width comparisons to conserve power and reduce the comparator's footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If full bit-width comparisons are used to monitor usage-based disturbance, then measurement precision is improved, but power consumption increases
Solution Approach 1:
The patent applies partial bit-width comparison instead of full bit-width comparison. The comparator only compares a subset of bits (e.g., most significant bits) rather than all bits of the activation count. This partial action approach maintains sufficient monitoring accuracy to detect substantially worse conditions while significantly reducing power consumption and computational resources required for the comparison operation.
2Measurement precision
If full bit-width comparisons are used to monitor usage-based disturbance, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent implements partial bit-width comparison that examines only a portion of the bits in the activation count (such as the most significant bits) rather than performing a complete bit-width comparison. This reduces the complexity and physical footprint of the comparator circuit while maintaining adequate precision for detecting substantially worse conditions that trigger refresh operations.
3Reliability
If frequent updates of worse-case conditions are performed, then reliability is improved, but power consumption increases
Solution Approach 1:
The patent implements periodic monitoring with threshold-based triggering. Instead of continuously or frequently updating the worse-case condition information, the system periodically checks whether new activation counts represent substantially worse conditions by comparing against a threshold. This periodic action with threshold filtering maintains data integrity by updating only when necessary while significantly reducing power consumption compared to frequent continuous updates.
4Reliability
If monitoring is performed continuously, then reliability is improved, but power consumption increases
Solution Approach 1:
The patent employs periodic monitoring rather than continuous monitoring. The system checks for substantially worse conditions at periodic intervals or triggered by specific events (such as row activations), rather than continuously monitoring all activation counts. This periodic approach maintains adequate disturbance detection capability while reducing power consumption by keeping the monitoring circuit inactive or in a low-power state between monitoring events.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively mitigates usage-based disturbance while reducing power consumption and physical space requirements, enhancing memory device efficiency and reliability.
Implementation Method 1
usage-based disturbance due to electromagnetic coupling between adjacent memory cells, leading to voltage fluctuations
Data Source
AI summary
Apparatuses and techniques are described implementing power-efficient monitoring for usage-based-disturbance mitigation. In a first aspect, a memory device takes a less strict approach for monitoring worse-case conditions associated with usage-based disturbance. In particular, the memory device conserves power by foregoing updating a list of rows associated with worse-case conditions until an unlisted row has a substantially worse condition than any one of the listed rows. This decreases how often the memory device expends power to update the list. In an optional second aspect, the memory device performs a partial bit-width comparison operation to evaluate the “substantially worse” criterion. The partial bit-width comparison enables a comparator to be implemented with a smaller footprint and operate with less power as compared to a comparator that is capable of performing a full bit-width comparison operation.