Memory Disturbance Recovery Mechanism Using Row-Level Warning Circuits
Solution Overview
Problem
Memory systems experience data deterioration and instability due to repeated accesses, leading to potential loss of data as bit values change, causing memory disturbances that existing technologies fail to effectively address.
Innovation Solution
A memory system with disturbance warning circuits and control logic that detects disturbance conditions in memory rows and performs recovery operations only when necessary, using recovery timing settings to optimize when recovery operations start, thereby reducing energy expenditure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If recovery operations are performed continuously on memory rows, then data integrity is maintained, but energy consumption increases significantly
Solution Approach 1:
The disturbance warning circuit performs preliminary detection of disturbance conditions in memory rows before actual data corruption occurs. When a disturbance condition is detected, the circuit triggers a recovery operation proactively, preventing data integrity issues while avoiding continuous recovery operations that would waste energy.
Solution Approach 2:
The disturbance warning circuit continuously monitors memory rows and provides feedback about disturbance conditions to the control logic. This feedback mechanism enables the system to perform recovery operations only when and where needed, rather than continuously across all memory rows, thus maintaining data integrity while reducing unnecessary energy consumption.
2Use of energy by moving object
If recovery operations are delayed, then energy consumption is reduced, but data stability deteriorates
Solution Approach 1:
The system performs recovery operations as a preliminary action before data corruption actually occurs. The disturbance warning circuit detects early signs of disturbance and triggers recovery proactively, ensuring data stability is maintained while avoiding delayed recovery that would compromise data integrity.
Solution Approach 2:
The disturbance warning circuit takes preliminary anti-action by detecting disturbance conditions and triggering recovery operations before data corruption can occur. This preemptive approach counteracts the deteriorating effect of disturbances on data stability while optimizing energy usage by acting only when necessary.
3Reliability
If disturbance detection is performed on all memory rows continuously, then data integrity is ensured, but system complexity and energy usage increase
Solution Approach 1:
The memory system is segmented into multiple independent memory rows, each with its own disturbance warning circuit. This segmentation allows the system to monitor and recover individual rows independently based on their specific disturbance conditions, rather than treating all memory uniformly, thus reducing overall system complexity and energy consumption.
Solution Approach 2:
Each memory row is equipped with its own disturbance warning circuit that autonomously monitors its own condition and triggers recovery operations when needed. This self-service approach eliminates the need for a centralized complex monitoring system, reducing overall system complexity while maintaining data integrity across all memory rows.
Data Source
AI summary
Components of a memory system, such as a memory controller and memory device, which detect accumulated memory read disturbances and correct such disturbances before they reach a level that causes errors. The memory device includes a memory array and a disturbance control circuit. The memory array includes a plurality of memory rows. Each memory row is associated with a disturbance warning circuit having a state that corresponds to an accumulated disturbance in the memory row. The disturbance control circuit determines, responsive to an activation of a memory row of the plurality of memory rows specified by a row access command, whether the disturbance condition is present in the memory row based on the state of the disturbance warning circuit associated with the memory row. If a disturbance condition is present, the disturbance control circuit causes a recovery operation to be performed on the memory row to reduce the accumulated disturbances.