Memory Device Program Disturbance Reduction via Self-Boosting

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Solution Overview

Problem

As semiconductor devices scale down, increasing integration in non-volatile memory leads to undesired coupling and interference between memory cells during programming, causing program disturbance and reducing data reliability.

Innovation Solution

A method for operating a memory device that involves applying specific voltage waveforms and recovery processes to reduce program disturbance by discharging excessive electrons from channel regions, establishing a self-boosting channel to minimize unintended programming of unselected cells.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the degree of integration of non-volatile memory is increased to enhance device performance and price competitiveness, then device performance and price competitiveness are improved, but undesired coupling and interference between memory cells during programming increases, causing program disturbance and reducing data reliability

Engineering Contradiction:
Improvedevice performanceVSAvoiddata reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent applies preliminary action by performing a recovery operation before the program operation. This recovery operation discharges excessive electrons from the channel region of unselected memory cells, preparing them in advance to prevent program disturbance during the subsequent programming process. The recovery voltage is applied to the bit line and word line to create a potential well that repels electrons from unselected cells before programming occurs.

Inventive Principle:
Principle #10Preliminary action

2Ease of manufacture

If voltage is applied to the selected word line to program the selected cell, then the selected cell is programmed, but other unselected cells on the same word line and other word lines are inadvertently programmed

Engineering Contradiction:
Improveprogramming operationVSAvoidprogram disturbance
Core Design Contradiction:
Ease of manufactureVSObject-generated harmful factors

Solution Approach 1:

The patent applies local quality by creating different voltage conditions in different regions of the memory array during programming. A recovery voltage is applied locally to unselected word lines and bit lines to create a potential well in the channel regions of unselected cells, while the selected cell receives the full program voltage. This localized voltage differentiation ensures that only the selected cell is programmed while unselected cells are protected through the recovered state.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The method effectively reduces program disturbance, enhancing data reliability by maintaining a maximal self-boosting voltage in program inhibited strings, thereby preventing inadvertent programming of unselected memory cells.

Implementation Method 1

applying specific voltage waveforms and recovery processes to reduce program disturbance by discharging excessive electrons from channel regions

Methodology Applied
Scientific EffectElectron discharge: Electrostatic Discharge

Implementation Method 2

establishing a self-boosting channel to minimize unintended programming of unselected cells

Methodology Applied
Scientific EffectSelf-boosting voltage effect:

Data Source

PatentEP3891747B1Method of reducing program disturbance in memory device and memory device utilizing same
Publication Date: 2023.08.09 YANGTZE MEMORY TECH CO LTD
  • EP3891747B1 patent drawingFigure 1
  • EP3891747B1 patent drawingFigure 2
  • EP3891747B1 patent drawingFigure 3

AI summary

A method of operating a memory device, the memory device includes a top select cell, a top dummy cell and a string of memory cells. The top select cell has a first terminal coupled to a bit line and a control terminal coupled to a top select line. The top dummy cell has a control terminal coupled to a top dummy word line. The string of memory cells has control terminals coupled to respective word lines, the method comprising: applying a pre-pulse voltage to the top dummy word line, the top select line and the bit line while applying a low voltage to the word lines, and then sequentially applying the low voltage to the top dummy word line, the top select line and the bit line while applying the low voltage to the word lines.