Semiconductor Memory DLL Clock Calibration
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Solution Overview
Problem
Conventional semiconductor memory devices lack active control over output AC parameters, leading to operation errors and system shutdowns due to fluctuations in power supply and temperature, especially as DRAM operation speeds increase, making it difficult to develop high-speed DRAMs.
Innovation Solution
A semiconductor memory device with a variable delay mechanism that adjusts the DLL clock and includes a calibration controller to actively control output AC parameters by measuring and calibrating the delay time based on measured parameter values, ensuring synchronized data and clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the operation speed of DRAM is increased, then the productivity is improved, but the output AC parameters become distorted due to power supply and temperature fluctuations, leading to operation errors
Solution Approach 1:
The patent implements a feedback mechanism where the memory device measures its own output AC parameters (tDQSQ, tDQSCK) and uses these measurements to adjust the DLL clock delay time. The calibration controller continuously monitors the actual output parameters and modifies the variable delay to maintain specification compliance, creating a closed-loop control system that adapts to power supply and temperature variations
Solution Approach 2:
The patent dynamically changes the delay parameter of the DLL clock based on measured output AC parameters. By adjusting the delay time variable in response to measured skew values, the system modifies temporal parameters to compensate for environmental variations, ensuring that output timing parameters remain within specifications despite changes in operating conditions
2Device complexity
If conventional DRAM modules are used without active control, then the device complexity is reduced, but the system shuts down when output AC parameters are distorted
Solution Approach 1:
The memory device performs self-calibration by measuring its own output AC parameters and automatically adjusting its internal delay parameters. The calibration controller within the memory device executes the calibration process without external intervention, enabling the device to self-correct timing skew and maintain reliable operation across varying conditions
Solution Approach 2:
The system implements internal feedback where measurement results of output AC parameters are fed back to the calibration controller, which then adjusts the variable delay accordingly. This closed-loop feedback mechanism enables automatic compensation for parameter drift without requiring external control systems
Data Source
AI summary
A semiconductor memory device includes: a variable delay for delaying a delay locked loop (DLL) clock by a predetermined delay time to output a delayed DLL clock; an output driver for outputting data and data strobe signal in response to the delayed DLL clock; and a calibration controller for controlling the predetermined delay time of the variable delay in response to output AC parameters.