Memory DLL Clock Buffer Control for Low Power-Down Current
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Solution Overview
Problem
Semiconductor memory devices struggle to keep up with the increasing operating speed of data processors, leading to inefficiencies in data input/output speed, and the delay locked loop (DLL) circuit consumes excessive current during power down modes, contributing to unnecessary power consumption.
Innovation Solution
A semiconductor memory device with a DLL circuit that includes a DLL clock buffer and a controller to generate a buffer enable signal using a code and clock enable signal, allowing for efficient delay locking operations and minimizing current consumption in power down modes by disabling unnecessary components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the DLL circuit is enabled during power down mode to maintain delay locking, then clock synchronization is maintained, but current consumption increases unnecessarily
Solution Approach 1:
The DLL circuit is enabled periodically - active during normal operation mode to maintain delay locking and clock synchronization, then disabled during power down mode to reduce current consumption. The mode register set controls the DLL enable signal based on the operational mode, creating a periodic on/off pattern that balances synchronization needs with power savings.
2Use of energy by moving object
If the DLL circuit is disabled during power down mode to reduce current consumption, then power usage decreases, but clock synchronization may be compromised upon mode switching
Solution Approach 1:
Before disabling the DLL circuit during power down mode transition, the system performs preliminary actions to save the current delay lock state. The mode register set is updated to reflect the power down mode, and when transitioning back to normal operation, the DLL circuit is re-enabled with the saved state, ensuring seamless clock synchronization without requiring full re-initialization.
3Manufacturing precision
If the DLL circuit operates continuously to maintain accurate delay locking, then data output synchronization is improved, but power consumption increases
Solution Approach 1:
The DLL circuit's operational state is made dynamic rather than static. It adapts its operation based on the memory device's operational mode - fully active during normal operation to ensure precise data output synchronization, and disabled during power down mode to reduce power consumption. This dynamic adaptation allows the system to optimize between precision and power usage based on real-time operational requirements.
Data Source
AI summary
A semiconductor memory device includes: a delay locked loop (DLL) clock buffer for buffering a system clock in response to the a buffer enable signal; a DLL circuit for generating a delay locked loop (DLL) clock by performing a delay locking operation using the buffered system clock; and a DLL clock buffer controller for generating the buffer enable signal in response to a code signal and a clock enable signal, the code signal containing information about whether to perform the delay locking operation.